u-boot.git/drivers/cpu, branch v2020.10 Unnamed repository; edit this file 'description' to name the repository. cpu: Convert the methods to use a const udevice * 2020-07-25T20:46:57+00:00 Simon Glass sjg@chromium.org 2020-01-27T05:06:27+00:00 961420fa5f3bcf837518e7f72d6f8c3ee090643d These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org> 
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" 2020-07-24T12:42:06+00:00 Tom Rini trini@konsulko.com 2020-07-24T12:42:06+00:00 7208396bbf1df1c7a85d263b7ff054e6b45d8240 This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> 
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
cpu: Convert the methods to use a const udevice * 2020-07-20T17:37:47+00:00 Simon Glass sjg@chromium.org 2020-01-27T05:06:27+00:00 f07e58b878fc18bd69d2c19075f0fb8d7d35da00 These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org> 
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
riscv: cpu: check and append L1 cache to cpu features 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:03+00:00 add0dc1f7de91112d9e738f9482b09b75fa86acb All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.

=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:02+00:00 b6b233ddb78205abc76dde60179bd129368dc3e8 The conditional check to read "mmu-type" from the device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in the device tree. The initialization of cpu features is now taken care in cpu-uclass driver, so no need to zero out cpu_freq in riscv_cpu driver and can be removed. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.

The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
uclass: cpu: fix to display proper CPU features 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:01+00:00 969251a5a4d3515abc233621bc8ca6f1c93d6dd4 The cmd "cpu detail" fetches uninitialized cpu feature information and thus displays wrong / inconsitent details as below. For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 The L1 cache or MMU entry seen above is also displayed inconsistently. So initialize cpu information to zero into cpu-uclass itself so that similar issues can be avoided for other CPU drivers. We now see correct features as: => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.

=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0

The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.

We now see correct features as:
=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
riscv: Enable cpu clock if it is present 2020-07-01T07:01:22+00:00 Sean Anderson seanga2@gmail.com 2020-06-24T10:41:22+00:00 627718626b05f715da555cc005426ab10f44bb98 The cpu clock is probably already enabled if we are executing code (though we could be executing from a different core). This patch prevents the cpu clock or its parents from being disabled. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
riscv: Try to get cpu frequency from a "clocks" node if it exists 2020-07-01T07:01:22+00:00 Sean Anderson seanga2@gmail.com 2020-06-24T10:41:21+00:00 ab24017a19b482d9026d21a2ec03416c5c4a388d Instead of always using the "clock-frequency" property to determine cpu frequency, try using a clock in "clocks" if it exists. This patch also fixes a bug where there could be spurious higher frequencies if sizeof(u32) != sizeof(ulong). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
cpu: imx8: use intended cpu-thermal device when getting temp value 2020-05-22T11:27:46+00:00 Anatolij Gustschin agust@denx.de 2020-05-19T23:31:44+00:00 74e8fb03bdafd096bcfaa36268376874dfb5c7d4 This fixes getting DT alert and critical pdata values in imx_scu_thermal driver. On i.MX8QXP using not initialized alert pdata value resulted in boot hang and endless loop outputting: CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting... While at it, preset CPU type values once to avoid multiple calls of device_is_compatible() for same property. Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> 
This fixes getting DT alert and critical pdata values in imx_scu_thermal
driver. On i.MX8QXP using not initialized alert pdata value resulted in
boot hang and endless loop outputting:
CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting...

While at it, preset CPU type values once to avoid multiple calls
of device_is_compatible() for same property.

Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
cpu: imx8: fix type and rate detection 2020-05-22T11:26:33+00:00 Anatolij Gustschin agust@denx.de 2020-05-16T20:34:19+00:00 69365540cf607d5212ebd014869e4f55c1de8044 CPU type and rate detection is broken, for A35 cpu we get A53: ... sc_pm_get_clock_rate: resource:0 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QXP RevB A53 at 0 MHz at 47C Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> 
CPU type and rate detection is broken, for A35 cpu we get A53:
...
sc_pm_get_clock_rate: resource:0 clk:2: res:3
Could not read CPU frequency: -22
CPU:   NXP i.MX8QXP RevB A53 at 0 MHz at 47C

Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>