u-boot.git/drivers/cpu, branch v2021.01 Unnamed repository; edit this file 'description' to name the repository. Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next 2020-10-05T14:54:27+00:00 Tom Rini trini@konsulko.com 2020-10-05T14:54:27+00:00 caebff09efe8c061b4d99b82262c67fb2db9bbcf First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM. 
First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
cpu: at91: add driver for CPU 2020-10-05T07:45:16+00:00 Claudiu Beznea claudiu.beznea@microchip.com 2020-10-01T10:27:25+00:00 01c35f269f21398fa9d1db1b90b73f7e95a3bf22 Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> 
Add basic CPU driver use to retrieve information about CPU itself.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
timer: Add a test for timer_timebase_fallback 2020-09-30T00:54:45+00:00 Sean Anderson seanga2@gmail.com 2020-09-28T14:52:23+00:00 7616e3687e447b5a838f472afb5275fe6a841f5b To test this function, sandbox CPU must set cpu_platdata.timebase_freq on bind. It also needs to expose a method to set the current cpu. I also make some most members of cpu_sandbox_ops static. On the timer side, the device tree property sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.

On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
cpu: Convert the methods to use a const udevice * 2020-07-25T20:46:57+00:00 Simon Glass sjg@chromium.org 2020-01-27T05:06:27+00:00 961420fa5f3bcf837518e7f72d6f8c3ee090643d These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org> 
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" 2020-07-24T12:42:06+00:00 Tom Rini trini@konsulko.com 2020-07-24T12:42:06+00:00 7208396bbf1df1c7a85d263b7ff054e6b45d8240 This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> 
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
cpu: Convert the methods to use a const udevice * 2020-07-20T17:37:47+00:00 Simon Glass sjg@chromium.org 2020-01-27T05:06:27+00:00 f07e58b878fc18bd69d2c19075f0fb8d7d35da00 These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org> 
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
riscv: cpu: check and append L1 cache to cpu features 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:03+00:00 add0dc1f7de91112d9e738f9482b09b75fa86acb All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.

=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:02+00:00 b6b233ddb78205abc76dde60179bd129368dc3e8 The conditional check to read "mmu-type" from the device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in the device tree. The initialization of cpu features is now taken care in cpu-uclass driver, so no need to zero out cpu_freq in riscv_cpu driver and can be removed. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.

The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
uclass: cpu: fix to display proper CPU features 2020-07-01T07:01:27+00:00 Sagar Shrikant Kadam sagar.kadam@sifive.com 2020-06-28T14:45:01+00:00 969251a5a4d3515abc233621bc8ca6f1c93d6dd4 The cmd "cpu detail" fetches uninitialized cpu feature information and thus displays wrong / inconsitent details as below. For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 The L1 cache or MMU entry seen above is also displayed inconsistently. So initialize cpu information to zero into cpu-uclass itself so that similar issues can be avoided for other CPU drivers. We now see correct features as: => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> 
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.

=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
        Microcode version 0x0
        Device ID 0x0

The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.

We now see correct features as:
=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
riscv: Enable cpu clock if it is present 2020-07-01T07:01:22+00:00 Sean Anderson seanga2@gmail.com 2020-06-24T10:41:22+00:00 627718626b05f715da555cc005426ab10f44bb98 The cpu clock is probably already enabled if we are executing code (though we could be executing from a different core). This patch prevents the cpu clock or its parents from being disabled. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>