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<title>u-boot.git/drivers/crypto/aspeed/Makefile, branch next</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>drivers/crypto: aspeed: Add Caliptra ECDSA384 support</title>
<updated>2024-10-21T23:52:52+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2024-10-14T09:56:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=936d4cb6eb4cb6ee611d0cf4f74b923f6593cbee'/>
<id>936d4cb6eb4cb6ee611d0cf4f74b923f6593cbee</id>
<content type='text'>
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export
an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use.

This patch is verified by the FIT signature verification using the
"sha384,ecdsa384" algorithm.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export
an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use.

This patch is verified by the FIT signature verification using the
"sha384,ecdsa384" algorithm.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto: aspeed: Add Caliptra SHA ACC support</title>
<updated>2024-09-16T22:37:17+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2024-08-30T07:23:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fca70d61817b9ad2fb4b4821b029e55f1945997b'/>
<id>fca70d61817b9ad2fb4b4821b029e55f1945997b</id>
<content type='text'>
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which
export a SHA accelerator interface for SoC to use.

Note that CPTRA 1.0 supports only SHA384 and SHA512 and this
patch is verified by the 'hash test sha384/sha512' commands.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
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<pre>
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which
export a SHA accelerator interface for SoC to use.

Note that CPTRA 1.0 supports only SHA384 and SHA512 and this
patch is verified by the 'hash test sha384/sha512' commands.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>crypto: aspeed: Add AST2600 ACRY support</title>
<updated>2021-11-17T22:05:00+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2021-10-27T06:17:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89c36cca0b697d80a6ed063b945d66cc59a761a8'/>
<id>89c36cca0b697d80a6ed063b945d66cc59a761a8</id>
<content type='text'>
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
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<pre>
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>crypto: aspeed: Add AST2600 HACE support</title>
<updated>2021-11-17T22:05:00+00:00</updated>
<author>
<name>Johnny Huang</name>
<email>johnny_huang@aspeedtech.com</email>
</author>
<published>2021-10-27T06:17:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9fcdd98e543abc0b5e7b1a2e05b995a5fbf1356d'/>
<id>9fcdd98e543abc0b5e7b1a2e05b995a5fbf1356d</id>
<content type='text'>
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang &lt;johnny_huang@aspeedtech.com&gt;
Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang &lt;johnny_huang@aspeedtech.com&gt;
Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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