u-boot.git/drivers/crypto/aspeed, branch next Unnamed repository; edit this file 'description' to name the repository. crypto: aspeed: Tighten some dependencies for the aspeed platforms 2025-07-10T14:41:00+00:00 Tom Rini trini@konsulko.com 2025-07-02T01:04:22+00:00 dbe1fa4d260fffd094d936c27d17bf4910bf2472 Some of the aspeed platform drivers cannot build without platform specific headers being available. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> 
Some of the aspeed platform drivers cannot build without platform
specific headers being available. Express those requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
drivers/crypto: aspeed: Add Caliptra ECDSA384 support 2024-10-21T23:52:52+00:00 Chia-Wei Wang chiawei_wang@aspeedtech.com 2024-10-14T09:56:20+00:00 936d4cb6eb4cb6ee611d0cf4f74b923f6593cbee Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use. This patch is verified by the FIT signature verification using the "sha384,ecdsa384" algorithm. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export
an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use.

This patch is verified by the FIT signature verification using the
"sha384,ecdsa384" algorithm.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/crypto: aspeed: Add Caliptra SHA ACC support 2024-09-16T22:37:17+00:00 Chia-Wei Wang chiawei_wang@aspeedtech.com 2024-08-30T07:23:34+00:00 fca70d61817b9ad2fb4b4821b029e55f1945997b Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export a SHA accelerator interface for SoC to use. Note that CPTRA 1.0 supports only SHA384 and SHA512 and this patch is verified by the 'hash test sha384/sha512' commands. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> 
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which
export a SHA accelerator interface for SoC to use.

Note that CPTRA 1.0 supports only SHA384 and SHA512 and this
patch is verified by the 'hash test sha384/sha512' commands.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" 2024-05-20T19:35:03+00:00 Tom Rini trini@konsulko.com 2024-05-20T19:35:03+00:00 03de305ec48b0bb28554372abb40ccd46dbe0bf9 As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" 2024-05-19T14:16:36+00:00 Tom Rini trini@konsulko.com 2024-05-19T02:20:43+00:00 d678a59d2d719da9e807495b4b021501f2836ca5 When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
crypto: Remove <common.h> and add needed includes 2024-05-07T14:00:41+00:00 Tom Rini trini@konsulko.com 2024-05-02T01:30:39+00:00 dcd59134c64ef369716cd2f78a8dbe765bec331d Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> 
Remove <common.h> from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
Correct SPL uses of HW_WATCHDOG 2023-02-10T12:41:39+00:00 Simon Glass sjg@chromium.org 2023-02-05T22:40:07+00:00 066640f3b8aec1d8463e0489cd489048996fd01d This converts 2 usages of this option to the non-SPL form, since there is no SPL_HW_WATCHDOG defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> 
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_HW_WATCHDOG defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
cyclic: Use schedule() instead of WATCHDOG_RESET() 2022-09-18T08:26:33+00:00 Stefan Roese sr@denx.de 2022-09-02T12:10:46+00:00 29caf9305b6fafe8f6d6b18fa1f825dff8686e61 Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm] 
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
crypto: aspeed: fix polling RSA status wrong issue 2022-02-21T13:35:40+00:00 Neal Liu neal_liu@aspeedtech.com 2022-02-15T10:14:40+00:00 829b41171b181e083fc984b72bb8acb31c1fb952 Check interrupt status to see if RSA engine is completed. After completion of the task, write-clear the status to finish operation. Add missing register base for completion. Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support") Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> 
Check interrupt status to see if RSA engine is completed. After completion
of the task, write-clear the status to finish operation.
Add missing register base for completion.

Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support")
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
crypto: aspeed: Add AST2600 ACRY support 2021-11-17T22:05:00+00:00 Chia-Wei Wang chiawei_wang@aspeedtech.com 2021-10-27T06:17:30+00:00 89c36cca0b697d80a6ed063b945d66cc59a761a8 ACRY is designed to accelerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> 
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>