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<title>u-boot.git/drivers/crypto/aspeed, branch v2023.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Correct SPL uses of HW_WATCHDOG</title>
<updated>2023-02-10T12:41:39+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-02-05T22:40:07+00:00</published>
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<id>066640f3b8aec1d8463e0489cd489048996fd01d</id>
<content type='text'>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_HW_WATCHDOG defined in Kconfig

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
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<pre>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_HW_WATCHDOG defined in Kconfig

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
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</entry>
<entry>
<title>cyclic: Use schedule() instead of WATCHDOG_RESET()</title>
<updated>2022-09-18T08:26:33+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2022-09-02T12:10:46+00:00</published>
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<id>29caf9305b6fafe8f6d6b18fa1f825dff8686e61</id>
<content type='text'>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Tom Rini &lt;trini@konsulko.com&gt; [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
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<pre>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Tom Rini &lt;trini@konsulko.com&gt; [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
</pre>
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</content>
</entry>
<entry>
<title>crypto: aspeed: fix polling RSA status wrong issue</title>
<updated>2022-02-21T13:35:40+00:00</updated>
<author>
<name>Neal Liu</name>
<email>neal_liu@aspeedtech.com</email>
</author>
<published>2022-02-15T10:14:40+00:00</published>
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<content type='text'>
Check interrupt status to see if RSA engine is completed. After completion
of the task, write-clear the status to finish operation.
Add missing register base for completion.

Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support")
Signed-off-by: Neal Liu &lt;neal_liu@aspeedtech.com&gt;
Reviewed-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
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<pre>
Check interrupt status to see if RSA engine is completed. After completion
of the task, write-clear the status to finish operation.
Add missing register base for completion.

Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support")
Signed-off-by: Neal Liu &lt;neal_liu@aspeedtech.com&gt;
Reviewed-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>crypto: aspeed: Add AST2600 ACRY support</title>
<updated>2021-11-17T22:05:00+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2021-10-27T06:17:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89c36cca0b697d80a6ed063b945d66cc59a761a8'/>
<id>89c36cca0b697d80a6ed063b945d66cc59a761a8</id>
<content type='text'>
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
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<pre>
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>crypto: aspeed: Add AST2600 HACE support</title>
<updated>2021-11-17T22:05:00+00:00</updated>
<author>
<name>Johnny Huang</name>
<email>johnny_huang@aspeedtech.com</email>
</author>
<published>2021-10-27T06:17:27+00:00</published>
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<id>9fcdd98e543abc0b5e7b1a2e05b995a5fbf1356d</id>
<content type='text'>
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang &lt;johnny_huang@aspeedtech.com&gt;
Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang &lt;johnny_huang@aspeedtech.com&gt;
Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
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