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<title>u-boot.git/drivers/crypto, branch v2016.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>drivers/crypto/fsl: fix endianness issue in RNG</title>
<updated>2015-12-15T00:57:35+00:00</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-12-08T08:24:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3a4800a5968f689788d70f7decb000a3d3e1a2f4'/>
<id>3a4800a5968f689788d70f7decb000a3d3e1a2f4</id>
<content type='text'>
For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
CC: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
CC: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>crypto/fsl: SEC driver cleanup for 64 bit and endianness</title>
<updated>2015-10-29T17:33:57+00:00</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@freescale.com</email>
</author>
<published>2015-10-29T17:28:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f59e69cbd38ff297a07687ba28437c257cd5757c'/>
<id>f59e69cbd38ff297a07687ba28437c257cd5757c</id>
<content type='text'>
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
   endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
   be depend on endianness of SEC block as 32 bit low and
   high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
   descriptor will vary depending on endianness of SEC.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
   endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
   be depend on endianness of SEC block as 32 bit low and
   high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
   descriptor will vary depending on endianness of SEC.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Correct License and Copyright information on few files</title>
<updated>2015-08-13T00:47:46+00:00</updated>
<author>
<name>Ruchika Gupta</name>
<email>ruchika.gupta@freescale.com</email>
</author>
<published>2015-07-27T03:37:39+00:00</published>
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<id>057c2200557e187a47f2c10af6c0b2db9bf88df3</id>
<content type='text'>
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license

Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
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<pre>
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license

Signed-off-by: Ruchika Gupta &lt;ruchika.gupta@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: hierarchize drivers Kconfig menu</title>
<updated>2015-08-13T00:47:44+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-07-25T17:46:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0b11dbf705ee294ac5a9fe1aeda7b7f5537a8d72'/>
<id>0b11dbf705ee294ac5a9fe1aeda7b7f5537a8d72</id>
<content type='text'>
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu.  Use hierarchic menu for each category.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu.  Use hierarchic menu for each category.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helper</title>
<updated>2015-08-03T19:06:38+00:00</updated>
<author>
<name>horia.geanta@freescale.com</name>
<email>horia.geanta@freescale.com</email>
</author>
<published>2015-07-08T14:24:58+00:00</published>
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<id>14d5547cf158c18bc340f01424e011b0802a6bb0</id>
<content type='text'>
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto/fsl: fix snooping for write transactions</title>
<updated>2015-08-03T19:06:38+00:00</updated>
<author>
<name>horia.geanta@freescale.com</name>
<email>horia.geanta@freescale.com</email>
</author>
<published>2015-07-08T14:24:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ef2412de6680c751abd39047cadff7e052a0f51'/>
<id>3ef2412de6680c751abd39047cadff7e052a0f51</id>
<content type='text'>
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.

For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU

Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Reviewed-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.

For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU

Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Reviewed-by: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Reviewed-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto/fsl: fix "era" property value on LE platforms</title>
<updated>2015-08-03T19:06:38+00:00</updated>
<author>
<name>horia.geanta@freescale.com</name>
<email>horia.geanta@freescale.com</email>
</author>
<published>2015-07-08T14:24:56+00:00</published>
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<id>e5d08b4d601d4060609b162f437327c823b00947</id>
<content type='text'>
Use fdt_setprop_u32() instead of fdt_setprop().

Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Reviewed-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
Use fdt_setprop_u32() instead of fdt_setprop().

Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă &lt;horia.geanta@freescale.com&gt;
Reviewed-by: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto/fsl: enable raw data instead of von Neumann data</title>
<updated>2015-08-03T19:06:37+00:00</updated>
<author>
<name>Alex Porosanu</name>
<email>alexandru.porosanu@freescale.com</email>
</author>
<published>2015-05-05T13:48:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c4065517362ae9132ceaaec4103ed5ad6c9cfe92'/>
<id>c4065517362ae9132ceaaec4103ed5ad6c9cfe92</id>
<content type='text'>
The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/crypto/fsl: disable RNG oscillator maximum frequency check</title>
<updated>2015-08-03T19:06:37+00:00</updated>
<author>
<name>Alex Porosanu</name>
<email>alexandru.porosanu@freescale.com</email>
</author>
<published>2015-05-05T13:48:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=026a3f1b7ca487bbce632060b8ca9193bb9edf87'/>
<id>026a3f1b7ca487bbce632060b8ca9193bb9edf87</id>
<content type='text'>
The rtfrqmax &amp; rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.

This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
The rtfrqmax &amp; rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.

This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.

Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Acked-by: Ruchika Gupta&lt;ruchika.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2015-03-06T01:50:30+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-03-05T21:41:04+00:00</published>
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<pre>
</pre>
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</entry>
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