u-boot.git/drivers/crypto, branch v2016.07

verified-boot: Minimal support for booting U-Boot proper from SPL

2016-06-12T17:14:58+00:00

This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.

The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256

In this example, SHA256 is the only selected hashing algorithm.

And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y

Signed-off-by: Teddy Reed 
Acked-by: Simon Glass 
Acked-by: Andreas Dannenberg 
Acked-by: Sumit Garg

crypto/fsl: add support for multiple SEC engines initialization

2016-05-18T15:51:46+00:00

For SoCs that contain multiple SEC engines, each of them needs
to be initialized (by means of initializing among others the
random number generator).

Signed-off-by: Alex Porosanu 
Reviewed-by: York Sun

armv8: LS2080A: Consolidate LS2080A and LS2085A

2016-04-06T17:26:46+00:00

LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun 
CC: Prabhakar Kushwaha 
Reviewed-by: Prabhakar Kushwaha

crypto/fsl: Make CAAM transactions cacheable

2016-03-29T15:46:22+00:00

This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as write back with write and
read allocate.

Signed-off-by: Saksham Jain 
Reviewed-by: York Sun

crypto/fsl: Correct 64-bit write when MMU disabled

2016-03-29T15:46:22+00:00

When MMU is disabled, 64-bit write must be aligned at 64-bit
boundary. Becaue the memory location is not guaranteed to be 64-bit
aligned, the 64-bit write needs to be split into two 32-bit writes
to avoid the alignment exception.

Signed-off-by: Aneesh Bansal 
Signed-off-by: Saksham Jain 
Reviewed-by: York Sun

drivers/crypto/fsl: define structures for PDB

2016-03-21T19:42:11+00:00

Structures are defined for PDB (Protocol Data Blcks) for various
operations. These structure will be used to add PDB data while
creating the PDB descriptors.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
CC: Ulises Cardenas 
Reviewed-by: York Sun

drivers/crypto/fsl: add constructs for protocol descriptors

2016-03-21T19:42:11+00:00

Construct APIs are added to create Protocol Descriptors for
CAAM block.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
CC: Ulises Cardenas 
Reviewed-by: York Sun

drivers/crypto/fsl: correct error checking in run_descriptor

2016-03-21T19:42:11+00:00

When CAAM runs a descriptor and an error occurs, a non-zero
value is set in Output Status Register. The if condition should
check the status for a non-zero value.

Signed-off-by: Aneesh Bansal 
Reviewed-by: York Sun

powerpc/SECURE_BOOT: Add PAMU driver

2016-02-24T16:40:55+00:00

PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.

The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.

The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.

Signed-off-by: Ruchika Gupta 
Signed-off-by: Aneesh Bansal 
Reviewed-by: York Sun

drivers/crypto/fsl : Allocate output ring with size aligned to CACHELNE SIZE

2016-02-24T16:40:55+00:00

The output ring needs to be invalidated before enqueuing the job to SEC.
While allocation of space to output ring, it should be taken care that the
size is cacheline size aligned inorder to prevent invalidating valid data.

The patch also correct the method of aligning end of structs while flushing caches

    Since start = align(start_of_struct), it is incorrect to assign
    end = align(start + struct_size). It should instead be,
    end = align(start_of_struct + struct_size).

Signed-off-by: Saksham Jain 
Signed-off-by: Ruchika Gupta 
Reviewed-by: York Sun