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<title>u-boot.git/drivers/ddr/altera/sequencer.c, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/altera/sequencer.c?h=v2020.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/altera/sequencer.c?h=v2020.01'/>
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<updated>2019-07-21T10:45:01Z</updated>
<entry>
<title>dm: ddr: socfpga: fix gen5 ddr driver to not use bss</title>
<updated>2019-07-21T10:45:01Z</updated>
<author>
<name>Simon Goldschmidt</name>
<email>simon.k.r.goldschmidt@gmail.com</email>
</author>
<published>2019-07-11T19:18:12Z</published>
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<id>urn:sha1:285b3cb939a8f70d5233fd12e0b9f840eac53812</id>
<content type='text'>
This driver uses bss from SPL board_init_f(). Change it to move all the
data from bss to a common struct allocated on the stack (64 byte).

In addition to saving 28 bytes of bss, the code even gets 264 bytes
smaller.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: move gen5 SDR driver to DM</title>
<updated>2019-04-17T20:20:16Z</updated>
<author>
<name>Simon Goldschmidt</name>
<email>simon.k.r.goldschmidt@gmail.com</email>
</author>
<published>2019-04-16T20:04:39Z</published>
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<id>urn:sha1:29873c74f367474faafd16376e2a9f404172fbdd</id>
<content type='text'>
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: silence PHY calibration unless in debug mode</title>
<updated>2018-01-25T08:59:37Z</updated>
<author>
<name>Goldschmidt Simon</name>
<email>sgoldschmidt@de.pepperl-fuchs.com</email>
</author>
<published>2018-01-25T06:04:44Z</published>
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<id>urn:sha1:92962b3caf17f5e64075601a466b3ac00dbd0a88</id>
<content type='text'>
This driver has been using printf() including filename since it was
added. Convert to using debug() instead.

Signed-off-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Repair DQ window centering code</title>
<updated>2016-04-20T09:28:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-05T21:17:35Z</published>
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<id>urn:sha1:e026b984e68cac45a8e18fc55dd48f1b75f91298</id>
<content type='text'>
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Staticize global variables</title>
<updated>2016-04-20T09:28:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-05T09:18:38Z</published>
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<id>urn:sha1:85f76628a05539699a4aeb0a511109d322293033</id>
<content type='text'>
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Make DLEVEL behavior inclusive</title>
<updated>2016-04-20T09:28:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-04T19:21:05Z</published>
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<id>urn:sha1:ea9aa2414e5c443e14ef7bef93210c17f629b7d6</id>
<content type='text'>
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Zero DM IN delay in scc_mgr_zero_group()</title>
<updated>2016-04-20T09:28:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-04T19:16:18Z</published>
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<id>urn:sha1:70ed80af46e58a25d472362fe5552e1e49eaf25b</id>
<content type='text'>
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Remove unnecessary ODT mode config</title>
<updated>2016-04-20T09:28:44Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-04T17:10:12Z</published>
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<id>urn:sha1:f3f777cdf00433866b1178e23a9a99e2eaf7d89e</id>
<content type='text'>
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Remove unnecessary update of the SCC</title>
<updated>2016-04-20T09:28:44Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-04T16:41:53Z</published>
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<id>urn:sha1:f5f8c411de0c1971475069ac011c858ca914eae7</id>
<content type='text'>
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
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