u-boot.git/drivers/ddr/altera, branch next

ddr: altera: Use dev_read_addr_index_ptr()

2026-08-19T16:36:04Z

Replace devfdt_get_addr_index_ptr() with dev_read_addr_index_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan

ddr: altera: Add delay before writing to MBRDADDR register

2026-08-19T16:36:03Z

Add a delay of 1ms before writing the address of the data for HIP interface into the Responder Mailbox Read Address Register. The UIBSSM mailbox require some time to settle down while waiting for the MBRDADATA_VALID bit to become 1 without this delay, specifically the board will timeout while waiting for MBRDDATA_VALID bit to 1 after setting to 1. This 1ms delay has been tested thoroughly and no intermittent issues with UIBSSM mailbox communication is observed. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Boon Khai Ng

ddr: altera: arria10: Fix incorrect address for mpu1

2026-08-19T16:36:03Z

SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS is already added in SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET() macro. Remove extra SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS in mpu1 address computation. Signed-off-by: Alif Zakuan Yuslaimi

ddr: socfpga: Implement ECC DRAM scrubbing support for both Gen5/Arria10

2026-08-19T16:36:03Z

Enable ECC scrubbing support for Gen5 by moving sdram_init_ecc_bits() from sdram_arria10.c to a new common file, sdram_soc32.c which is shared by both Arria10 and Gen5 devices. This makes ECC scrubbing support no longer exclusive only to Arria10. Remove legacy HW watchdog check in favor of current WDT DM for Gen5/Arria10. New Kconfig is introduced to enable this implementation only on the default Arria10 and CycloneV boards as this will increase the SPL size which will exceed some Gen5 devices' SPL size limit. Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi

ddr: altera: gen5: Add DRAM size checking

2026-08-19T16:36:03Z

Add DRAM size checking compare between size from device tree and actual hardware. Trigger hang if DRAM size from device tree is greater than actual hardware. Display warning message if DRAM size mismatch between device tree and actual hardware. get_ram_size() uses size from device tree. So, it has consistency with other device families. New Kconfig is introduced to enable this implementation only on the default CycloneV board as this will increase the SPL size which will exceed some Gen5 devices' SPL size limit. Signed-off-by: Alif Zakuan Yuslaimi

ddr: altera: soc64: Add secure region support for ATF flow

2026-08-19T15:07:05Z

Setting up firewall regions based on SDRAM memory banks configuration (up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space. First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region, other address spaces are non-secure regions. The ARM Trusted Firmware (ATF) image is located in this first 1 MiB memory region. So, this can prevent software executing at non-secure state EL0-EL2 and non-secure masters access to secure region. Add common function for firewall setup and reuse for all SoC64 devices. Signed-off-by: Alif Zakuan Yuslaimi

arm: socfpga: Move firmware register settings from source code to device tree

2026-08-19T15:07:04Z

Migrate the CCU, firewall, and high privilege register configurations from hardcoded values in the source code to the device tree. L4 per/sys firewall setup which was previously done by firewall_setup() in spl_s10.c is now replaced by DTreg node in socfpga_soc64_u-boot.dtsi as Stratix10 is sharing the same tables that Agilex uses. This helps to centralize hardware configuration, improves maintainability, and allows easier customization for different platforms. Signed-off-by: Alif Zakuan Yuslaimi

treewide: move bi_dram[] from bd to gd

2026-06-25T00:13:24Z

Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP)

Replace TARGET namespace and cleanup properly

2026-02-14T17:06:46Z

TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile

drivers: ddr: altera: iossm_mailbox: widen MEM_TOTAL_CAPACITY mask

2026-02-14T17:06:46Z

The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits, which could truncate DDR size values on larger-memory systems. Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent the full capacity field according to the hardware specification. Signed-off-by: Naresh Kumar Ravulapalli Signed-off-by: Chen Huei Lok Reviewed-by: Tien Fong Chee Best regards,