u-boot.git/drivers/ddr/altera, branch next

treewide: move bi_dram[] from bd to gd

2026-06-25T00:13:24Z

Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP)

Replace TARGET namespace and cleanup properly

2026-02-14T17:06:46Z

TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile

drivers: ddr: altera: iossm_mailbox: widen MEM_TOTAL_CAPACITY mask

2026-02-14T17:06:46Z

The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits, which could truncate DDR size values on larger-memory systems. Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent the full capacity field according to the hardware specification. Signed-off-by: Naresh Kumar Ravulapalli Signed-off-by: Chen Huei Lok Reviewed-by: Tien Fong Chee Best regards,

ddr: altera: arria10: Add DRAM size checking

2026-02-14T17:06:46Z

Add DRAM size checking compare between size from device tree and actual hardware. Trigger hang if DRAM size from device tree is greater than actual hardware. Display warning message if DRAM size mismatch between device tree and actual hardware. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee Best regards,

drivers: ddr: altera: Correct DDR calibration status check

2025-09-30T06:29:53Z

Bit 3 of the seq2core register is no longer set to indicate calibration completion. Instead, added polling of the seq2core register until it reads 0b00000111, signaling that the Nios processor has started the calibration process. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

drivers: ddr: altera: Check IOSSM mailbox compatibility

2025-09-30T06:29:53Z

Compatibility check of IOSSM mailbox with U-Boot is performed by verifying the mailbox specification version. If check fails, appropriate error message is displayed. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

ddr: altera: soc64: Fix dram size calculation in clamshell mode

2025-08-08T14:20:54Z

Fix wrong memory size calculation in clamshell mode Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: soc64: Clean up bit-shift by zero bit

2025-08-08T14:20:54Z

Clean up bit-shift by zero bit Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: Add DDR driver for Agilex7 M-series

2025-08-08T14:20:54Z

This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: Add uibssm mailbox support for Agilex7 M-series with HBM

2025-08-08T14:20:53Z

Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB and HBM subsystem through software defined mailbox interface. HPS can retrieve HBM memory interface calibration status, UIB configuration, memory interfae configuration, trigger calibration and etc with the list of supported mailbox command type and opcode. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee