u-boot.git/drivers/ddr/altera, branch v2018.05

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12Z

When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini

Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR

2018-04-27T18:54:48Z

We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini

ddr: altera: silence PHY calibration unless in debug mode

2018-01-25T08:59:37Z

This driver has been using printf() including filename since it was added. Convert to using debug() instead. Signed-off-by: Simon Goldschmidt

arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig

2017-04-14T12:06:57Z

Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan

ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-10-27T06:03:07Z

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen

ddr: altera: Repair DQ window centering code

2016-04-20T09:28:45Z

The code uses a lot of signed numbers, which ended up in variables of unsigned type, which resulted in all sorts of underflows. This in turn caused incorrect calibration on certain boards. Moreover, repair the readout of the DQ delay, which was being pulled from wrong register. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

ddr: altera: Staticize global variables

2016-04-20T09:28:45Z

Just staticize global variables in sequencer, since there is no point in having these symbols available outside of the DDR code. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

ddr: altera: Make DLEVEL behavior inclusive

2016-04-20T09:28:45Z

Originally, the DLEVEL selects the debug level within the sequencer code, but only displays the messages on that particular debug level. Tweak the handling such that for particular debug level, debug messages on that level and lower are displayed. This allows better regulation of debug message verbosity. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

2016-04-20T09:28:45Z

This one last set of delay configuration registers was not properly zeroed out originally, fix it and zero them out. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

ddr: altera: Remove unnecessary ODT mode config

2016-04-20T09:28:44Z

There is no point in resetting the ODT setting if the write test failed, since the code will always retry the calibration and thus reconfigure the ODT anyway OR the code will fail calibration and halt. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See