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<title>u-boot.git/drivers/ddr/altera, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/altera?h=v2018.07</id>
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<updated>2018-05-20T13:47:45Z</updated>
<entry>
<title>SPDX: Fixup SPDX tags in a few new files</title>
<updated>2018-05-20T13:47:45Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-20T13:47:45Z</published>
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<id>urn:sha1:624d2cae3401c2e4d43c571a9b81d1f650e7703d</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>configs: Add DDR Kconfig support for Arria 10</title>
<updated>2018-05-18T08:30:47Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-12-05T07:58:03Z</published>
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<id>urn:sha1:901af3e903c09c7681197a03367d82286f9f6e3f</id>
<content type='text'>
This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: Add DDR driver for Arria 10</title>
<updated>2018-05-18T08:30:47Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-12-05T07:58:02Z</published>
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<id>urn:sha1:5658a299bdd2f616277eaea5d601976108d18326</id>
<content type='text'>
Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: Rename the gen5 sdram driver to more specific name</title>
<updated>2018-05-18T08:30:47Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-12-05T07:58:00Z</published>
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<id>urn:sha1:9ef9fe3455557161d076a821f0a65ee490198931</id>
<content type='text'>
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR</title>
<updated>2018-04-27T18:54:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-04-18T17:50:47Z</published>
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<id>urn:sha1:d024236e5a31a2b4b82cbcc98b31b8170fc88d28</id>
<content type='text'>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: silence PHY calibration unless in debug mode</title>
<updated>2018-01-25T08:59:37Z</updated>
<author>
<name>Goldschmidt Simon</name>
<email>sgoldschmidt@de.pepperl-fuchs.com</email>
</author>
<published>2018-01-25T06:04:44Z</published>
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<id>urn:sha1:92962b3caf17f5e64075601a466b3ac00dbd0a88</id>
<content type='text'>
This driver has been using printf() including filename since it was
added. Convert to using debug() instead.

Signed-off-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig</title>
<updated>2017-04-14T12:06:57Z</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2017-04-05T09:32:51Z</published>
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<id>urn:sha1:707cd012e2e1dbed7150f7908727abb7bdc4c1a7</id>
<content type='text'>
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Configuring SDRAM extra cycles timing parameters</title>
<updated>2016-10-27T06:03:07Z</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2016-09-21T02:25:56Z</published>
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<id>urn:sha1:89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd</id>
<content type='text'>
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Repair DQ window centering code</title>
<updated>2016-04-20T09:28:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-04-05T21:17:35Z</published>
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<id>urn:sha1:e026b984e68cac45a8e18fc55dd48f1b75f91298</id>
<content type='text'>
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
</content>
</entry>
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