u-boot.git/drivers/ddr/altera, branch v2019.04

ddr: socfpga: Clean up ddr_setup()

2019-03-09T22:25:19Z

Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: socfpga: Clean up EMIF reset

2019-03-09T22:25:19Z

The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: socfpga: Fix EMIF clear timeout

2019-03-09T22:25:19Z

The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: socfpga: Fix newline in debug print on A10

2019-03-09T16:59:13Z

The debug print is missing a newline, add it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: socfpga: Fix IO in Arria10 DDR driver

2019-03-09T16:59:13Z

The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee

socfpga: stratix10: fix sdram_calculate_size

2018-09-15T01:17:01Z

Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen

ddr: altera: Add ECC DRAM scrubbing support for Arria10

2018-07-12T07:22:12Z

The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen

ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

2018-07-12T07:22:12Z

This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen

ddr: altera: stratix10: Add DDR support for Stratix10 SoC

2018-07-12T07:22:12Z

Add DDR support for Stratix SoC Signed-off-by: Chin Liang See Signed-off-by: Ley Foon Tan

SPDX: Fixup SPDX tags in a few new files

2018-05-20T13:47:45Z

Signed-off-by: Tom Rini