u-boot.git/drivers/ddr/altera, branch v2020.01

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55Z

These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

ddr: socfpga: gen5: constify altera_gen5_sdram_ops

2019-11-20T21:32:00Z

Make the function pointer struct const, as it does not need to be writable. This doesn't really change anything other than moving this variable to a different section. No functional change. Signed-off-by: Simon Goldschmidt Reviewed-by: Ley Foon Tan

dm: ddr: socfpga: fix gen5 ddr driver to not use bss

2019-07-21T10:45:01Z

This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt

arm: socfpga: Move Stratix 10 SDRAM driver to DM

2019-05-06T10:44:17Z

Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan

ddr: altera: Compile ALTERA SDRAM in SPL only

2019-05-06T10:44:17Z

Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan

ddr: altera: Stratix10: Add ECC memory scrubbing

2019-04-17T20:20:17Z

Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan

ddr: altera: Stratix10: Add multi-banks DRAM size check

2019-04-17T20:20:17Z

Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan

ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

2019-04-17T20:20:17Z

Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan

arm: socfpga: move gen5 SDR driver to DM

2019-04-17T20:20:16Z

To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt

ddr: socfpga: Clean up ddr_setup()

2019-03-09T22:25:19Z

Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee