u-boot.git/drivers/ddr/altera, branch v2022.04

drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".

2022-01-13T12:57:50Z

WS cleanup: remove trailing empty lines

2021-09-30T12:08:56Z

Signed-off-by: Wolfgang Denk

ddr: altera: use KBUILD_BASENAME instead of FILE

2021-09-22T19:31:05Z

The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: altera: Add SDRAM driver for Intel N5X device

2021-08-25T05:47:05Z

The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim Signed-off-by: Tien Fong Chee

ddr: socfpga: Enable memory test on memory size less than 1GB

2021-08-25T05:43:51Z

Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee

arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64

2021-03-08T02:59:10Z

Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim

dm: ddr: socfpga: don't assign values that are not used

2021-02-24T21:51:49Z

The values of left_edge[0] and right_edge[0] are overwritten before they are used. Remove the superfluous assignments. Fixes: 285b3cb939a8 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss") Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42Z

Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include at all, so remove that include. Signed-off-by: Simon Glass Signed-off-by: Tom Rini

dm: Use access methods for dev/uclass private data

2021-01-05T19:24:40Z

Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass Acked-by: Andy Shevchenko Acked-by: Pratyush Yadav

dm: treewide: Rename ..._platdata variables to just ..._plat

2020-12-13T23:51:09Z

Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass