u-boot.git/drivers/ddr/altera, branch v2023.04

cyclic: Use schedule() instead of WATCHDOG_RESET()

2022-09-18T08:26:33Z

Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese Reviewed-by: Simon Glass Tested-by: Tom Rini [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]

ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched

2022-06-17T08:27:05Z

Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee

ddr: altera: Stratix10: Use phys_size_t for memory size

2022-06-16T08:10:58Z

Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee

ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS

2022-06-16T08:10:44Z

Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee

intel: n5x: ddr: update license

2022-06-15T09:48:22Z

All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee

drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".

2022-01-13T12:57:50Z

WS cleanup: remove trailing empty lines

2021-09-30T12:08:56Z

Signed-off-by: Wolfgang Denk

ddr: altera: use KBUILD_BASENAME instead of FILE

2021-09-22T19:31:05Z

The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee

ddr: altera: Add SDRAM driver for Intel N5X device

2021-08-25T05:47:05Z

The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim Signed-off-by: Tien Fong Chee

ddr: socfpga: Enable memory test on memory size less than 1GB

2021-08-25T05:43:51Z

Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee