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<title>u-boot.git/drivers/ddr/altera, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/altera?h=v2024.04</id>
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<updated>2023-12-21T13:54:37Z</updated>
<entry>
<title>global: Drop common.h inclusion</title>
<updated>2023-12-21T13:54:37Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-14T18:16:47Z</published>
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<id>urn:sha1:cb3ce954013ce383e64b73b65df1eb4ef8833570</id>
<content type='text'>
In order to make it easier to move on to dropping common.h from code
directly, remove common.h inclusion from the rest of the header file
which had been including it.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>drivers: use devfdt_get_addr_index_ptr when cast to pointer</title>
<updated>2023-05-06T09:28:18Z</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-03-13T00:32:31Z</published>
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<id>urn:sha1:320a1938b6f7ea1ad89f7e18c7fef5898f98fc5b</id>
<content type='text'>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>cyclic: Use schedule() instead of WATCHDOG_RESET()</title>
<updated>2022-09-18T08:26:33Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2022-09-02T12:10:46Z</published>
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<id>urn:sha1:29caf9305b6fafe8f6d6b18fa1f825dff8686e61</id>
<content type='text'>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Tom Rini &lt;trini@konsulko.com&gt; [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
</content>
</entry>
<entry>
<title>ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched</title>
<updated>2022-06-17T08:27:05Z</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@intel.com</email>
</author>
<published>2022-06-01T10:49:02Z</published>
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<id>urn:sha1:32e0379143b433e29d76404f5f4c279067e48853</id>
<content type='text'>
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Stratix10: Use phys_size_t for memory size</title>
<updated>2022-06-16T08:10:58Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-04-27T04:52:42Z</published>
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<id>urn:sha1:39bbcc341bda435899cb623a19d20727ca98c67a</id>
<content type='text'>
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Ignore bit[7-4] for both seq2core &amp; core2seq handshake in HPS</title>
<updated>2022-06-16T08:10:44Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-04-27T04:27:21Z</published>
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<id>urn:sha1:ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4</id>
<content type='text'>
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>intel: n5x: ddr: update license</title>
<updated>2022-06-15T09:48:22Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2022-06-10T11:18:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=166e5b82a3f49239f67ac5f0d6df8abeb6ca0bdd'/>
<id>urn:sha1:166e5b82a3f49239f67ac5f0d6df8abeb6ca0bdd</id>
<content type='text'>
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".</title>
<updated>2022-01-13T12:57:50Z</updated>
<author>
<name>Vagrant Cascadian</name>
<email>vagrant@debian.org</email>
</author>
<published>2021-12-21T21:07:01Z</published>
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<id>urn:sha1:0776c5fbb7d3693d69796fc811f3040644e3576b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>WS cleanup: remove trailing empty lines</title>
<updated>2021-09-30T12:08:56Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2021-09-27T15:42:36Z</published>
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<id>urn:sha1:66356b4c06c934021f6cb58d93877427162b369f</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>ddr: altera: use KBUILD_BASENAME instead of __FILE__</title>
<updated>2021-09-22T19:31:05Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2021-09-14T03:20:19Z</published>
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<id>urn:sha1:532010da67329a1c3dbe92a167486df6e61d4f4a</id>
<content type='text'>
The KBUILD_BASENAME contains just the name of the compiled module,
in this case 'sequencer', rather than a full path to the compiled
file. Use it to prevent pulling the full path into the U-Boot binary,
which is useless and annoying.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
Cc: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Cc: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
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