u-boot.git/drivers/ddr/altera, branch v2026.04

drivers: ddr: altera: Correct DDR calibration status check

2025-09-30T06:29:53Z

Bit 3 of the seq2core register is no longer set to indicate calibration completion. Instead, added polling of the seq2core register until it reads 0b00000111, signaling that the Nios processor has started the calibration process. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

drivers: ddr: altera: Check IOSSM mailbox compatibility

2025-09-30T06:29:53Z

Compatibility check of IOSSM mailbox with U-Boot is performed by verifying the mailbox specification version. If check fails, appropriate error message is displayed. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

ddr: altera: soc64: Fix dram size calculation in clamshell mode

2025-08-08T14:20:54Z

Fix wrong memory size calculation in clamshell mode Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: soc64: Clean up bit-shift by zero bit

2025-08-08T14:20:54Z

Clean up bit-shift by zero bit Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: Add DDR driver for Agilex7 M-series

2025-08-08T14:20:54Z

This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: Add uibssm mailbox support for Agilex7 M-series with HBM

2025-08-08T14:20:53Z

Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB and HBM subsystem through software defined mailbox interface. HPS can retrieve HBM memory interface calibration status, UIB configuration, memory interfae configuration, trigger calibration and etc with the list of supported mailbox command type and opcode. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: agilex: Get ACF from boot scratch register

2025-08-08T14:20:49Z

The DDR data rate must be set correctly in the DDRIOCTRL register according to the Actual Clock Frequency (ACF) value. By enabling the reading of ACF value from bit 18 of the boot scratch register during initialization, the DDR data rate is able to be configured accurately. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: agilex: Remove code redundancy

2025-08-08T14:20:48Z

Remove redundant code for MPFE CSR firewall disabled as this was already set in DTreg dts. Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: soc64: Add secure region support for ATF flow

2025-08-08T14:20:48Z

Setting up firewall regions based on SDRAM memory banks configuration (up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space. First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region, other address spaces are non-secure regions. The ARM Trusted Firmware (ATF) image is located in this first 1 MiB memory region. So, this can prevent software executing at non-secure state EL0-EL2 and non-secure masters access to secure region. Add common function for firewall setup and reuse for all SoC64 devices. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: n5x: size_t cannot be less than 0

2025-07-30T09:45:29Z

The function socfpga_get_handoff_size returns an int so make the struct fields used to accept the return value also an int so that testing for less than 0 is then valid. This issue was found by Smatch. Signed-off-by: Andrew Goodbody