u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2014.04

driver/ddr: Add 256 byte interleaving support

2014-02-21T16:06:13Z

Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun

driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

2014-02-21T16:06:13Z

Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun

powerpc/mpc8xxx: Extend DDR registers' fields

2013-11-25T19:43:46Z

Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun

Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx

2013-11-25T19:43:46Z

Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun

Driver/DDR: Moving Freescale DDR driver to a common driver

2013-11-25T19:43:43Z

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun