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<title>u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2014.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/ctrl_regs.c?h=v2014.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/ctrl_regs.c?h=v2014.07'/>
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<updated>2014-06-05T20:45:07Z</updated>
<entry>
<title>powerpc/mpc85xx: Add workaround for DDR erratum A004508</title>
<updated>2014-06-05T20:45:07Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-05-23T20:15:00Z</published>
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<id>urn:sha1:9855b3beca648dabe4d86b06d36bf219ebd0732d</id>
<content type='text'>
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr: Fix possible out of bounds error</title>
<updated>2014-04-23T00:58:49Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-04-01T21:20:49Z</published>
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<id>urn:sha1:349689b8021f0a7d7923099bd8bbe5eab117d4fa</id>
<content type='text'>
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add DDR4 support to Freescale DDR driver</title>
<updated>2014-04-23T00:58:48Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-03-28T00:54:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85'/>
<id>urn:sha1:34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85</id>
<content type='text'>
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr: Add 256 byte interleaving support</title>
<updated>2014-02-21T16:06:13Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-02-10T21:59:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6b1e1254f326940e5b65c7029f71b964bdf28fd4'/>
<id>urn:sha1:6b1e1254f326940e5b65c7029f71b964bdf28fd4</id>
<content type='text'>
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr: Change Freescale ARM DDR driver to support both big and little endian</title>
<updated>2014-02-21T16:06:13Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-02-10T21:59:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4e5b1bd0dff216b00d7ce9a5201dfe173805a06c'/>
<id>urn:sha1:4e5b1bd0dff216b00d7ce9a5201dfe173805a06c</id>
<content type='text'>
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc8xxx: Extend DDR registers' fields</title>
<updated>2013-11-25T19:43:46Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-06-03T19:39:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d4263b8adb5bd940c95cbaebaa0da9eaf759bfed'/>
<id>urn:sha1:d4263b8adb5bd940c95cbaebaa0da9eaf759bfed</id>
<content type='text'>
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.

TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx</title>
<updated>2013-11-25T19:43:46Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-11-18T18:29:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9a17eb5b7e7ba528c278a9677c38d7ae722d93ec'/>
<id>urn:sha1:9a17eb5b7e7ba528c278a9677c38d7ae722d93ec</id>
<content type='text'>
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Driver/DDR: Moving Freescale DDR driver to a common driver</title>
<updated>2013-11-25T19:43:43Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-09-30T16:22:09Z</published>
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<id>urn:sha1:5614e71b4956c579cd4419b958b33fa6316eaa92</id>
<content type='text'>
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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