u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2015.01

driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

2014-12-15T17:15:12Z

For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun

driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

2014-12-05T16:06:11Z

Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: York Sun

linux/kernel.h: sync min, max, min3, max3 macros with Linux

2014-11-23T11:48:30Z

U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada Acked-by: Pavel Machek Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini

driver/ddr/fsl: Fix DDR4 driver

2014-09-25T15:36:20Z

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun

driver/ddr/fsl: Fix tXP and tCKE

2014-09-25T15:36:18Z

The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun

driver/ddr/fsl: Add support of overriding chip select write leveling

2014-09-08T17:30:34Z

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun

driver/ddr/freescale: Add support of accumulate ECC

2014-09-08T17:30:34Z

If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun

driver/ddr: Fix DDR register timing_cfg_8

2014-07-22T23:25:55Z

The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun

powerpc/mpc85xx: Add workaround for DDR erratum A004508

2014-06-05T20:45:07Z

When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun

drivers/ddr: Fix possible out of bounds error

2014-04-23T00:58:49Z

This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun Reviewed-by: York Sun