u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2015.07

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23T15:55:53Z

CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53Z

Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun

MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register

2015-04-20T17:15:28Z

According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune Reviewed-by: York Sun

driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation

2015-02-24T21:09:26Z

wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24T21:09:18Z

Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun

driver/ddr/fsl: Adjust CAS to preamble override for emulator

2015-02-24T21:09:02Z

On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun

driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

2014-12-15T17:15:12Z

For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun

driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

2014-12-05T16:06:11Z

Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: York Sun

linux/kernel.h: sync min, max, min3, max3 macros with Linux

2014-11-23T11:48:30Z

U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada Acked-by: Pavel Machek Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini

driver/ddr/fsl: Fix DDR4 driver

2014-09-25T15:36:20Z

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun