u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2016.07

drivers/ddr/fsl: Fix timing_cfg_2 register

2016-06-03T21:12:06Z

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

2016-06-03T21:06:35Z

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

2016-03-21T19:42:13Z

Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Update timing config for heavy load

2015-12-14T02:27:27Z

In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun

driver/ddr/fsl: Update MR5 RTT park

2015-12-14T02:27:27Z

For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun

driver/ddr/fsl: Update DDR4 MR6 for Vref range

2015-12-14T02:27:27Z

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun

drivers/ddr/fsl_ddr: Make SR_IE configurable

2015-10-30T16:19:41Z

SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund Reviewed-by: York Sun

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23T15:55:53Z

CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53Z

Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun

MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register

2015-04-20T17:15:28Z

According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune Reviewed-by: York Sun