u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2016.09

driver/ddr/fsl: Fix timing_cfg_2

2016-08-02T16:47:34Z

Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun Reported-by: Thomas Schaefer

Various, unrelated tree-wide typo fixes.

2016-07-16T13:43:12Z

Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day

drivers/ddr/fsl: Fix timing_cfg_2 register

2016-06-03T21:12:06Z

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

2016-06-03T21:06:35Z

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

2016-03-21T19:42:13Z

Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Update timing config for heavy load

2015-12-14T02:27:27Z

In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun

driver/ddr/fsl: Update MR5 RTT park

2015-12-14T02:27:27Z

For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun

driver/ddr/fsl: Update DDR4 MR6 for Vref range

2015-12-14T02:27:27Z

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun

drivers/ddr/fsl_ddr: Make SR_IE configurable

2015-10-30T16:19:41Z

SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund Reviewed-by: York Sun

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23T15:55:53Z

CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun