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<title>u-boot.git/drivers/ddr/fsl/ctrl_regs.c, branch v2018.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/ctrl_regs.c?h=v2018.03</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/ctrl_regs.c?h=v2018.03'/>
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<updated>2018-02-15T02:34:05Z</updated>
<entry>
<title>Revert "drivers/ddr/fsl: Dual-license DDR driver"</title>
<updated>2018-02-15T02:34:05Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-02-15T02:34:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ac727577f0f84991e0cae999f175174e606027e2'/>
<id>urn:sha1:ac727577f0f84991e0cae999f175174e606027e2</id>
<content type='text'>
Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Dual-license DDR driver</title>
<updated>2018-02-09T16:36:40Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-02-07T19:47:22Z</published>
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<id>urn:sha1:ee3556bcafbb05e59aabdc31368984e76acaabc4</id>
<content type='text'>
To make this driver easier to be reused, dual-license DDR driver.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: Tom Rini &lt;trini@konsulko.com&gt;
CC: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
CC: Thomas Schaefer &lt;thomas.schaefer@kontron.com&gt;
CC: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
CC: Robert P. J. Day &lt;rpjday@crashcourse.ca&gt;
CC: Alexander Merkle &lt;alexander.merkle@lauterbach.com&gt;
CC: Joakim Tjernlund &lt;joakim.tjernlund@transmode.se&gt;
CC: Curt Brune &lt;curt@cumulusnetworks.com&gt;
CC: Valentin Longchamp &lt;valentin.longchamp@keymile.com&gt;
CC: Wolfgang Denk &lt;wd@denx.de&gt;
CC: Anatolij Gustschin &lt;agust@denx.de&gt;
CC: Ira W. Snyder &lt;iws@ovro.caltech.edu&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
CC: Sebastien Carlier &lt;sebastien.carlier@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
CC: Peter Tyser &lt;ptyser@xes-inc.com&gt;
CC: Paul Gortmaker &lt;paul.gortmaker@windriver.com&gt;
CC: Peter Tyser &lt;ptyser@xes-inc.com&gt;
CC: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Add calculation of register control words</title>
<updated>2018-01-30T17:14:07Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T18:24:08Z</published>
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<id>urn:sha1:564e9383e53b567114bd3403246c0759a6d69c50</id>
<content type='text'>
DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Add 3DS RDIMM support</title>
<updated>2018-01-30T17:14:07Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T17:44:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c0c32af0b2f037e3e167c7ac82e7110ebae48fb5'/>
<id>urn:sha1:c0c32af0b2f037e3e167c7ac82e7110ebae48fb5</id>
<content type='text'>
On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Fix DDR4 RDIMM support</title>
<updated>2018-01-30T17:14:06Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T17:44:33Z</published>
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<id>urn:sha1:426230a65f2dd62c3b6c1509e9775d5500db20d3</id>
<content type='text'>
For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>common: arm: freescale: layerscape: Move header files out of common.h</title>
<updated>2017-06-05T18:12:59Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:23:10Z</published>
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<id>urn:sha1:457e51cffdacf117c2afdd09d9bfc2f8df7314cb</id>
<content type='text'>
We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: freescale: Move arch-specific declarations</title>
<updated>2017-06-05T16:30:55Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:23:06Z</published>
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<id>urn:sha1:6e2941d787819ae1221d7f8295fa67d2ba94a913</id>
<content type='text'>
The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Fixup thinko defined(FSL_LSCH3) -&gt; defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS</title>
<updated>2017-01-05T00:40:52Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:45Z</published>
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<id>urn:sha1:51370d561842ae7438337e77a93177e13796ac45</id>
<content type='text'>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum</title>
<updated>2016-12-05T16:31:45Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@nxp.com</email>
</author>
<published>2016-11-21T03:36:48Z</published>
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<id>urn:sha1:02fb2761576be8096ebf1b3f961a2cdb21b422ae</id>
<content type='text'>
- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>powerpc: MPC8555: Remove macro CONFIG_MPC8555</title>
<updated>2016-11-24T07:42:05Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-11-16T19:23:23Z</published>
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<id>urn:sha1:3c3d8ab58d40d39830de7aed3f4b7110067d7d2d</id>
<content type='text'>
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
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