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<title>u-boot.git/drivers/ddr/fsl/interactive.c, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/interactive.c?h=v2016.03</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/interactive.c?h=v2016.03'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2015-04-23T15:55:53Z</updated>
<entry>
<title>driver/ddr/fsl: Fix driver to support empty first slot</title>
<updated>2015-04-23T15:55:53Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2015-03-19T16:30:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6b95be228024c7d15b9164b59187ef02333bb0c8'/>
<id>urn:sha1:6b95be228024c7d15b9164b59187ef02333bb0c8</id>
<content type='text'>
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Update DDR driver for DDR4</title>
<updated>2015-04-23T15:55:53Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2015-03-19T16:30:26Z</published>
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<id>urn:sha1:66869f955417b89dbf6b7cbb72738b2205a26bf8</id>
<content type='text'>
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Fix tXP and tCKE</title>
<updated>2014-09-25T15:36:18Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-08-21T23:13:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bb5783224b9b12eecf406761f82e3de2a2ca9dae'/>
<id>urn:sha1:bb5783224b9b12eecf406761f82e3de2a2ca9dae</id>
<content type='text'>
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add support of overriding chip select write leveling</title>
<updated>2014-09-08T17:30:34Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-09-05T05:52:43Z</published>
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<id>urn:sha1:ef87cab66492fe530bb6ec2e499b030c5ae60286</id>
<content type='text'>
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Fix printing unspecified module info for DDR4</title>
<updated>2014-06-05T20:45:07Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-06-05T19:32:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=353527d527b78297571c05b8a1687c92d42f6d20'/>
<id>urn:sha1:353527d527b78297571c05b8a1687c92d42f6d20</id>
<content type='text'>
The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Add cli_ prefix to readline functions</title>
<updated>2014-05-29T21:45:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-04-11T02:01:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e1bf824dfd6881f6f633238c275bfa1e5d83c433'/>
<id>urn:sha1:e1bf824dfd6881f6f633238c275bfa1e5d83c433</id>
<content type='text'>
This makes it clear where the code resides.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>move CLI prototypes to cli.h and add comments</title>
<updated>2014-05-29T21:45:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-04-11T02:01:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=18d66533ac773f59efc93e5c19971fad5e6af82f'/>
<id>urn:sha1:18d66533ac773f59efc93e5c19971fad5e6af82f</id>
<content type='text'>
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add DDR4 support to Freescale DDR driver</title>
<updated>2014-04-23T00:58:48Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-03-28T00:54:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85'/>
<id>urn:sha1:34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85</id>
<content type='text'>
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>Driver/DDR: Moving Freescale DDR driver to a common driver</title>
<updated>2013-11-25T19:43:43Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-09-30T16:22:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5614e71b4956c579cd4419b958b33fa6316eaa92'/>
<id>urn:sha1:5614e71b4956c579cd4419b958b33fa6316eaa92</id>
<content type='text'>
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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