u-boot.git/drivers/ddr/fsl/interactive.c, branch v2017.09

env: Rename getenv/_f() to env_get()

2017-08-16T12:30:24Z

We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk Signed-off-by: Simon Glass

driver: ddr: fsl: Fix compiling error for DDR2

2017-06-12T18:30:00Z

Fix compiling error of "no member named 'taamin_ps'" for DDR2. Signed-off-by: York Sun

ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS

2017-01-05T00:40:52Z

These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun

driver/ddr/fsl: Add more debug registers

2016-09-14T21:05:32Z

32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun Signed-off-by: Shengzhou Liu

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23T15:55:53Z

CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53Z

Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun

driver/ddr/fsl: Fix tXP and tCKE

2014-09-25T15:36:18Z

The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun

driver/ddr/fsl: Add support of overriding chip select write leveling

2014-09-08T17:30:34Z

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun

driver/ddr/fsl: Fix printing unspecified module info for DDR4

2014-06-05T20:45:07Z

The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun

Add cli_ prefix to readline functions

2014-05-29T21:45:31Z

This makes it clear where the code resides. Signed-off-by: Simon Glass