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<title>u-boot.git/drivers/ddr/fsl/interactive.c, branch v2018.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/interactive.c?h=v2018.03</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl/interactive.c?h=v2018.03'/>
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<updated>2018-02-15T02:34:05Z</updated>
<entry>
<title>Revert "drivers/ddr/fsl: Dual-license DDR driver"</title>
<updated>2018-02-15T02:34:05Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-02-15T02:34:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ac727577f0f84991e0cae999f175174e606027e2'/>
<id>urn:sha1:ac727577f0f84991e0cae999f175174e606027e2</id>
<content type='text'>
Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Dual-license DDR driver</title>
<updated>2018-02-09T16:36:40Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-02-07T19:47:22Z</published>
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<id>urn:sha1:ee3556bcafbb05e59aabdc31368984e76acaabc4</id>
<content type='text'>
To make this driver easier to be reused, dual-license DDR driver.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: Tom Rini &lt;trini@konsulko.com&gt;
CC: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
CC: Thomas Schaefer &lt;thomas.schaefer@kontron.com&gt;
CC: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
CC: Robert P. J. Day &lt;rpjday@crashcourse.ca&gt;
CC: Alexander Merkle &lt;alexander.merkle@lauterbach.com&gt;
CC: Joakim Tjernlund &lt;joakim.tjernlund@transmode.se&gt;
CC: Curt Brune &lt;curt@cumulusnetworks.com&gt;
CC: Valentin Longchamp &lt;valentin.longchamp@keymile.com&gt;
CC: Wolfgang Denk &lt;wd@denx.de&gt;
CC: Anatolij Gustschin &lt;agust@denx.de&gt;
CC: Ira W. Snyder &lt;iws@ovro.caltech.edu&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
CC: Sebastien Carlier &lt;sebastien.carlier@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
CC: Peter Tyser &lt;ptyser@xes-inc.com&gt;
CC: Paul Gortmaker &lt;paul.gortmaker@windriver.com&gt;
CC: Peter Tyser &lt;ptyser@xes-inc.com&gt;
CC: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Cleanup unused variable</title>
<updated>2018-01-30T17:14:07Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T17:44:38Z</published>
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<id>urn:sha1:140ad2d8991ca31d0e84af5119c74fc6e2c5a2d4</id>
<content type='text'>
Variable "row_density" is no longer used. Drop it from DIMM structure.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Add 3DS RDIMM support</title>
<updated>2018-01-30T17:14:07Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T17:44:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c0c32af0b2f037e3e167c7ac82e7110ebae48fb5'/>
<id>urn:sha1:c0c32af0b2f037e3e167c7ac82e7110ebae48fb5</id>
<content type='text'>
On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: Fix DDR4 RDIMM support</title>
<updated>2018-01-30T17:14:06Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2018-01-29T17:44:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=426230a65f2dd62c3b6c1509e9775d5500db20d3'/>
<id>urn:sha1:426230a65f2dd62c3b6c1509e9775d5500db20d3</id>
<content type='text'>
For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>env: Rename getenv/_f() to env_get()</title>
<updated>2017-08-16T12:30:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-08-03T18:22:12Z</published>
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<id>urn:sha1:00caae6d47645e68d6e5277aceb69592b49381a6</id>
<content type='text'>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>driver: ddr: fsl: Fix compiling error for DDR2</title>
<updated>2017-06-12T18:30:00Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2017-05-26T00:03:23Z</published>
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<id>urn:sha1:7c8e0e052853a181e379735f25cfe85dfb575e1c</id>
<content type='text'>
Fix compiling error of "no member named 'taamin_ps'" for DDR2.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS</title>
<updated>2017-01-05T00:40:52Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:45Z</published>
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<id>urn:sha1:51370d561842ae7438337e77a93177e13796ac45</id>
<content type='text'>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add more debug registers</title>
<updated>2016-09-14T21:05:32Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-08-29T09:04:12Z</published>
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<id>urn:sha1:b406731aa9861591352f274f5744c7cb003b9677</id>
<content type='text'>
32 more debug registers are added for newer DDR controllers.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Fix driver to support empty first slot</title>
<updated>2015-04-23T15:55:53Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2015-03-19T16:30:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6b95be228024c7d15b9164b59187ef02333bb0c8'/>
<id>urn:sha1:6b95be228024c7d15b9164b59187ef02333bb0c8</id>
<content type='text'>
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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