u-boot.git/drivers/ddr/fsl/util.c, branch v2016.09

Add more SPDX-License-Identifier tags

2016-01-19T13:31:21Z

In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

2015-11-30T17:11:11Z

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53Z

Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun

driver/ddr/fsl: Add sync of refresh

2015-02-24T21:09:42Z

Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24T21:09:18Z

Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun

driver/ddr: Restruct driver to allow standalone memory space

2014-09-25T15:36:18Z

U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

2014-04-23T00:58:48Z

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun

driver/ddr: Add 256 byte interleaving support

2014-02-21T16:06:13Z

Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun

driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

2014-02-21T16:06:13Z

Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun

Driver/DDR: Add Freescale DDR driver for ARM

2013-11-25T19:43:46Z

Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun