u-boot.git/drivers/ddr/fsl, branch v2015.04

driver/ddr/fsl: Add sync of refresh

2015-02-24T21:09:42Z

Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun

driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation

2015-02-24T21:09:26Z

wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24T21:09:18Z

Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun

driver/ddr/fsl: Add workround for erratumn A008514

2015-02-24T21:09:10Z

Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun

driver/ddr/fsl: Add workaround for A008336

2015-02-24T21:09:06Z

Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun

driver/ddr/fsl: Adjust CAS to preamble override for emulator

2015-02-24T21:09:02Z

On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun

arm/ls1021a: Add workaround for DDR erratum A008378

2015-01-24T04:29:13Z

Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun

driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

2014-12-15T17:15:12Z

For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun

fsl/sleep: updated the deep sleep framework for QorIQ platforms

2014-12-11T17:41:18Z

With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for faulty SPD

2014-12-05T16:06:14Z

Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun