u-boot.git/drivers/ddr/fsl, branch v2016.01-rc2

drivers/ddr/fsl: Fix typo in BIST test for DDR4

2015-11-30T17:11:12Z

BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun Reported-by: Shengzhou Liu

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

2015-11-30T17:11:11Z

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun

armv8: ls2085a: Add support of LS2085A SoC

2015-11-30T17:10:47Z

Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun

armv8: LS2080A: Rename LS2085A to reflect LS2080A

2015-11-30T16:53:04Z

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun

Various Makefiles: Add SPDX-License-Identifier tags

2015-11-10T14:19:52Z

After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart Signed-off-by: Tom Rini

drivers/ddr/fsl_ddr: Make SR_IE configurable

2015-10-30T16:19:41Z

SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund Reviewed-by: York Sun

drivers/ddr/fsl: Adjust bstopre value

2015-08-03T19:06:38Z

By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: York Sun

driver/ddr/fsl: Add a hook to update SPD address

2015-07-20T18:44:35Z

In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha

driver/ddr/fsl: Add workaround for DDR erratum A008511

2015-04-23T15:55:54Z

This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun

driver/ddr/fsl: Add built-in memory test for DDR4 driver

2015-04-23T15:55:53Z

Add built-in memory test to catch errors after DDR is initialized, before any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST. An environmental variable "ddr_bist" is checked before starting test. It takes a while (several seconds) depending on system memory size. Signed-off-by: York Sun