u-boot.git/drivers/ddr/fsl, branch v2016.03

drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers

2016-01-25T16:24:16Z

Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for A009663

2016-01-25T16:24:15Z

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

fsl/ddr: Add workaround for ERRATUM_A009942

2016-01-25T16:24:14Z

During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

Add more SPDX-License-Identifier tags

2016-01-19T13:31:21Z

In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini

move erratum a008336 and a008514 to soc specific file

2015-12-15T00:57:32Z

As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao Reviewed-by: York Sun

fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

2015-12-14T02:27:28Z

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Update timing config for heavy load

2015-12-14T02:27:27Z

In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun

driver/ddr/fsl: Update workaround for A008511 for vref range

2015-12-14T02:27:27Z

The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun

driver/ddr/fsl: Update MR5 RTT park

2015-12-14T02:27:27Z

For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun

driver/ddr/fsl: Update DDR4 MR6 for Vref range

2015-12-14T02:27:27Z

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun