<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/ddr/fsl, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl?h=v2016.05</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr/fsl?h=v2016.05'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-03-27T13:12:23Z</updated>
<entry>
<title>Fix typo choosen in comments and printf logs</title>
<updated>2016-03-27T13:12:23Z</updated>
<author>
<name>Alexander Merkle</name>
<email>alexander.merkle@lauterbach.com</email>
</author>
<published>2016-03-17T14:44:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd8d8da3d768fe232f11fe8f90c0bbb7c7812e80'/>
<id>urn:sha1:dd8d8da3d768fe232f11fe8f90c0bbb7c7812e80</id>
<content type='text'>
Minor change: chosen is written with one "o".
No code change here, only comment &amp; printf.

Signed-off-by: Alexander Merkle &lt;alexander.merkle@lauterbach.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add workaround for erratum A-009803</title>
<updated>2016-03-21T19:42:13Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@nxp.com</email>
</author>
<published>2016-03-10T09:36:57Z</published>
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<id>urn:sha1:dd8e740c789350fadeb9a13ab367380da2b9b42f</id>
<content type='text'>
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete</title>
<updated>2016-03-21T19:42:13Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@nxp.com</email>
</author>
<published>2016-03-10T09:36:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eb118807a4c1778bda6294c36e379711cb08e198'/>
<id>urn:sha1:eb118807a4c1778bda6294c36e379711cb08e198</id>
<content type='text'>
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers</title>
<updated>2016-01-25T16:24:16Z</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@nxp.com</email>
</author>
<published>2016-01-14T18:28:04Z</published>
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<id>urn:sha1:81dfdee0dc6c6ca6bdf0c75e0903afefc950d512</id>
<content type='text'>
Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Add workaround for A009663</title>
<updated>2016-01-25T16:24:15Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-12-16T08:45:41Z</published>
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<id>urn:sha1:a994b3deb00bf3177cdf9f92060baec4f640f466</id>
<content type='text'>
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>fsl/ddr: Add workaround for ERRATUM_A009942</title>
<updated>2016-01-25T16:24:14Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2016-01-06T03:26:51Z</published>
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<id>urn:sha1:0d3972cfcd6dff18d110d2ee01ad99e3623bfd45</id>
<content type='text'>
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Add more SPDX-License-Identifier tags</title>
<updated>2016-01-19T13:31:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-01-15T03:05:13Z</published>
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<id>urn:sha1:5b8031ccb4ed6e84457d883198d77efc307085dc</id>
<content type='text'>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>move erratum a008336 and a008514 to soc specific file</title>
<updated>2015-12-15T00:57:32Z</updated>
<author>
<name>Yao Yuan</name>
<email>yao.yuan@freescale.com</email>
</author>
<published>2015-12-05T06:59:14Z</published>
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<id>urn:sha1:000f4e7686f4291fbd74d8920b586caf10f9241f</id>
<content type='text'>
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao &lt;yao.yuan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>fsl/ddr: updated ddr errata-A008378 for arm and power SoCs</title>
<updated>2015-12-14T02:27:28Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2015-11-20T07:52:04Z</published>
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<id>urn:sha1:a46b1852de967f8a7de26e0b46e864c794a18c16</id>
<content type='text'>
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>driver/ddr/fsl: Update timing config for heavy load</title>
<updated>2015-12-14T02:27:27Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2015-11-04T18:03:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3'/>
<id>urn:sha1:6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3</id>
<content type='text'>
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
</feed>
