u-boot.git/drivers/ddr/imx/imx8m, branch master

drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:48Z

Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

ddr: Remove and add needed includes

2024-05-07T14:00:41Z

Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini

imx8m: fix reading of DDR4 MR registers [again]

2022-10-24T09:34:33Z

Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version actually seems to work in practice. However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c, copied most of the rest of ddrphy_utils.c to drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused file)]. I assume this must have broken the imx8mm-cl-iot-gate board, at least those that have not had their eeprom programmed with the proper information. It certainly did break our out-of-tree board which always reads back the ID register and uses that for a sanity check. So apply the fix from 290ffe5788 once again. Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) Signed-off-by: Rasmus Villemoes Reviewed-by: Fabio Estevam

imx8m: ddrphy_utils: Remove unused file

2022-09-18T20:56:10Z

The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c , this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the deduplication was implemented and was not removed. Remove it as it is unused. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan

ddr: imx: Add i.MX9 DDR controller driver

2022-07-26T09:29:01Z

Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li Signed-off-by: Peng Fan

imx8m: fix reading of DDR4 MR registers

2022-05-20T07:30:28Z

I was trying to employ lpddr4_mr_read() to something similar to what the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c differs from the private one used by that board in how it extracts the byte value, and I was only getting zeroes. Adding a bit of debug printf'ing gives me tmp = 0x00ffff00 tmp = 0x00070700 tmp = 0x00000000 tmp = 0x00101000 and indeed I was expecting a (combined) value of 0xff070010 (0xff being Manufacturer ID for Micron). I can't find any documentation that says how the values are supposed to be read, but clearly the iot-gate definition is the right one, both for its use case as well as my imx8mp-based board. So lift the private definition of lpddr4_mr_read() from the imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration in the ddr.h header where e.g. get_trained_CDD() is already declared. This has only been compile-tested for the imx8mm-cl-iot-gate board (since I don't have the hardware), but since I've merely moved its definition of lpddr4_mr_read(), I'd be surprised if it changed anything for that board. Signed-off-by: Rasmus Villemoes Tested-by: Ying-Chun Liu (PaulLiu) Reviewed-by: Fabio Estevam

imx8m: ddrphy_utils: Add 3732 MT/s mode

2022-04-12T13:36:17Z

Add entry for 3732 MT/s mode of operation of the LPDDR4, in which case the DDR PLL has to be configured in 933 MHz mode. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam

imx8mp: refine power on imx8mp board

2021-04-08T07:18:29Z

VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng Signed-off-by: Peng Fan