u-boot.git/drivers/ddr/imx/imx8ulp, branch master

drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:48+00:00

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03+00:00

As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36+00:00

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

ddr: Remove and add needed includes

2024-05-07T14:00:41+00:00

Remove  from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini

Kconfig: Remove trailing whitespace in its prompt

2024-04-22T17:01:48+00:00

All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or
trailing whitespace in its prompt

Signed-off-by: Michal Simek

ddr: imx: Update the ddr init flow on imx8ulp

2023-03-29T18:15:42+00:00

Update the ddr init flow to support LPDDR3 and PLL bypass mode.

Signed-off-by: Jacky Bai 
Reviewed-by: Ye Li

ddr: imx8ulp: Change DRAM timing save area to 0x20055000

2023-03-29T18:15:42+00:00

To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware

Signed-off-by: Ye Li 
Reviewed-by: Jacky Bai

imx8ulp: ddr: Fix DDR frequency request issue

2022-02-05T12:38:39+00:00

After acking the requested frequency, should wait the ack bit clear
by DDR controller and check the DFS interrupt for next request polling.
Otherwise, the next polling of request bit will get previous value
that DDR controller have not cleared it, so a wrong request frequency
is used.

Reviewed-by: Peng Fan 
Signed-off-by: Ye Li 
Signed-off-by: Peng Fan

imx8ulp:ddr: saving the dram config timing data into sram

2022-02-05T12:38:39+00:00

On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.

Reviewed-by: Ye Li 
Signed-off-by: Jacky Bai 
Signed-off-by: Peng Fan

ddr: Add DDR driver for iMX8ULP

2021-08-09T12:46:51+00:00

Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.

When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init

Signed-off-by: Ye Li