u-boot.git/drivers/ddr, branch master Unnamed repository; edit this file 'description' to name the repository. Replace TARGET namespace and cleanup properly 2026-02-14T17:06:46+00:00 Tien Fong Chee tien.fong.chee@altera.com 2026-02-13T12:27:23+00:00 62f7a94602094617ac384839ed695c2906893a88 TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune <briansune@gmail.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> # Conflicts: # drivers/ddr/altera/Makefile 
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.

Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

# Conflicts:
#	drivers/ddr/altera/Makefile
drivers: ddr: altera: iossm_mailbox: widen MEM_TOTAL_CAPACITY mask 2026-02-14T17:06:46+00:00 Naresh Kumar Ravulapalli nareshkumar.ravulapalli@altera.com 2026-02-09T02:07:09+00:00 cb23bbf4d7403dbfe1e4b4ef80bca6ae585a181e The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits, which could truncate DDR size values on larger-memory systems. Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent the full capacity field according to the hardware specification. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards, 
The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits,
which could truncate DDR size values on larger-memory systems.

Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent
the full capacity field according to the hardware specification.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards,
ddr: altera: arria10: Add DRAM size checking 2026-02-14T17:06:46+00:00 Alif Zakuan Yuslaimi alif.zakuan.yuslaimi@altera.com 2025-12-16T08:46:22+00:00 847e67582b1f0eee85e8f1aa7f5a7a3a41286288 Add DRAM size checking compare between size from device tree and actual hardware. Trigger hang if DRAM size from device tree is greater than actual hardware. Display warning message if DRAM size mismatch between device tree and actual hardware. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards, 
Add DRAM size checking compare between size from device tree and actual
hardware.

Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards,
Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next 2025-09-30T22:11:23+00:00 Tom Rini trini@konsulko.com 2025-09-30T22:11:23+00:00 aff68c8514858ddd8d2e508d47bede566511521b SoCFPGA updates for v2025.10: CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762 This pull request brings a set of updates across SoCFPGA platforms covering Agilex5, Agilex7, N5X, and Stratix10. The changes include: * Agilex5 enhancements: - USB3.1 enablement and DWC3 host driver support - System Manager register configuration for USB3 - Watchdog timeout increase and SDMMC clock API integration - dcache handling improvements in SMC mailbox path - Enable SPL_SYS_DCACHE_OFF in defconfig * Clock driver improvements: - Introduce dt-bindings header for Agilex clocks - Add enable/disable API and EMAC clock selection fixes - Replace manual shifts with FIELD_GET usage * DDR updates: - IOSSM mailbox compatibility check - Correct DDR calibration status handling * Device tree changes: - Agilex5: disable cache allocation for reads - Stratix10: add NAND IP node - Enable driver model watchdog - Enable USB3.1 node for Agilex5 * Config cleanups: - Simplify Agilex7 VAB defconfig - Remove obsolete SYS_BOOTM_LEN from N5X VAB config - Enable CRC32 support for SoCFPGA - Increase USB hub debounce timeout Overall this set improves reliability of DDR and cache flows, adds missing USB and MMC features for Agilex5, and refines clock and configuration handling across platforms. This patch set has been tested on Agilex 5 devkit, and Agilex devkit. 
SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
drivers: ddr: altera: Correct DDR calibration status check 2025-09-30T06:29:53+00:00 Naresh Kumar Ravulapalli nareshkumar.ravulapalli@altera.com 2025-08-08T09:42:42+00:00 63ef1c7a7391e7440bdfbffedd2cc5d9007707cd Bit 3 of the seq2core register is no longer set to indicate calibration completion. Instead, added polling of the seq2core register until it reads 0b00000111, signaling that the Nios processor has started the calibration process. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: ddr: altera: Check IOSSM mailbox compatibility 2025-09-30T06:29:53+00:00 Naresh Kumar Ravulapalli nareshkumar.ravulapalli@altera.com 2025-08-08T09:36:59+00:00 5d2ef97c66f0a432c859cfdf64ef696017619ad6 Compatibility check of IOSSM mailbox with U-Boot is performed by verifying the mailbox specification version. If check fails, appropriate error message is displayed. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Compatibility check of IOSSM mailbox with U-Boot is performed
by verifying the mailbox specification version. If check fails,
appropriate error message is displayed.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ddr: fsl: Provide initial value for zqcs_init 2025-08-27T07:39:05+00:00 Andrew Goodbody andrew.goodbody@linaro.org 2025-07-24T15:32:55+00:00 377159bfb8ee35ce16200818cfa55cdfba8c69e9 In the case of !zq_en zqcs_init is never assigned to although its value is used. Correct by initialising zqcs_init to 0. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
In the case of !zq_en zqcs_init is never assigned to although its value
is used. Correct by initialising zqcs_init to 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
ddr: altera: soc64: Fix dram size calculation in clamshell mode 2025-08-08T14:20:54+00:00 Tingting Meng tingting.meng@altera.com 2025-08-04T01:24:58+00:00 4face059c1ea1d7eb10470307526de7a9a3aecd4 Fix wrong memory size calculation in clamshell mode Signed-off-by: Tingting Meng <tingting.meng@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Fix wrong memory size calculation in clamshell mode

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ddr: altera: soc64: Clean up bit-shift by zero bit 2025-08-08T14:20:54+00:00 Tingting Meng tingting.meng@altera.com 2025-08-04T01:24:57+00:00 e5bc1aee5e3b5f90697ff528e05a6a8ff481f15b Clean up bit-shift by zero bit Signed-off-by: Tingting Meng <tingting.meng@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Clean up bit-shift by zero bit

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ddr: altera: Add DDR driver for Agilex7 M-series 2025-08-08T14:20:54+00:00 Tingting Meng tingting.meng@altera.com 2025-08-04T01:24:56+00:00 0b5376b34a8232cd878452574c0e60235ddaf1e7 This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Tingting Meng <tingting.meng@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>