u-boot.git/drivers/ddr, branch next

imx9: Add support for saving DDR training data to NVM

2026-05-15T20:31:39+00:00

DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.

U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.

On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.

Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.

Signed-off-by: Viorel Suman 
Signed-off-by: Ye Li 
Signed-off-by: Simona Toaca

imx8mq: Correct signed_hdmi firmware position

2026-04-21T23:49:39+00:00

signed_hdmi_imx8m.bin is already signed and has a IVT header. It should not
be put in u-boot-spl-mkimage.signed.bin. Move it to head of flash.bin
following NXP imx-mkimage. Keeping it in u-boot-spl-mkimage.signed.bin also
consumes a lot of TCM space which is not expected.

While moving it to head of flash.bin, other changes are required,
u-boot.itb is put at sector 768 per defconfig, so u-boot.itb binman
offset should be updated and it should be moved out from binman section.

Also binman symbol address are updated, so need to subtract u-boot-spl
image_pos + CONFIG_SPL_TEXT_BASE to find the correct location of ddr phy
firmware.

Because there is 1KB padding in HDMI firmware, use 32KB when burning
flash.bin to sd card.

Signed-off-by: Peng Fan

drivers: ddr: imx: Fix Kconfig for SAVED_DRAM_TIMING_BASE

2026-04-21T23:49:39+00:00

The 'default' directive should be before 'help'.

Signed-off-by: Simona Toaca 
Reviewed-by: Marek Vasut

Replace TARGET namespace and cleanup properly

2026-02-14T17:06:46+00:00

TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.

Signed-off-by: Brian Sune 
Reviewed-by: Tien Fong Chee 

# Conflicts:
#	drivers/ddr/altera/Makefile

drivers: ddr: altera: iossm_mailbox: widen MEM_TOTAL_CAPACITY mask

2026-02-14T17:06:46+00:00

The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits,
which could truncate DDR size values on larger-memory systems.

Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent
the full capacity field according to the hardware specification.

Signed-off-by: Naresh Kumar Ravulapalli 
Signed-off-by: Chen Huei Lok 
Reviewed-by: Tien Fong Chee  Best regards,

ddr: altera: arria10: Add DRAM size checking

2026-02-14T17:06:46+00:00

Add DRAM size checking compare between size from device tree and actual
hardware.

Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.

Signed-off-by: Alif Zakuan Yuslaimi 
Reviewed-by: Tien Fong Chee  Best regards,

Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

2025-09-30T22:11:23+00:00

SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.

drivers: ddr: altera: Correct DDR calibration status check

2025-09-30T06:29:53+00:00

Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli 
Reviewed-by: Tien Fong Chee

drivers: ddr: altera: Check IOSSM mailbox compatibility

2025-09-30T06:29:53+00:00

Compatibility check of IOSSM mailbox with U-Boot is performed
by verifying the mailbox specification version. If check fails,
appropriate error message is displayed.

Signed-off-by: Naresh Kumar Ravulapalli 
Reviewed-by: Tien Fong Chee

ddr: fsl: Provide initial value for zqcs_init

2025-08-27T07:39:05+00:00

In the case of !zq_en zqcs_init is never assigned to although its value
is used. Correct by initialising zqcs_init to 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody 
Signed-off-by: Peng Fan