u-boot.git/drivers/ddr, branch v2014.04

driver/ddr: Add 256 byte interleaving support

2014-02-21T16:06:13+00:00

Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun

Driver/ddr: Add support of different DDR base address

2014-02-21T16:06:13+00:00

DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun

driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

2014-02-21T16:06:13+00:00

Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun

powerpc/mpc85xx: Revise workaround for DDR-A003

2014-01-21T21:40:52+00:00

Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.

This patch also restores two debug registers changed by the workaround.

Signed-off-by: York Sun 
CC: Ben Collins 
CC: James Yang

Driver/DDR: Update DDR driver to allow non-zero base address

2013-11-25T19:43:47+00:00

The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.

Signed-off-by: York Sun

powerpc/mpc8xxx: Extend DDR registers' fields

2013-11-25T19:43:46+00:00

Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.

TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.

Signed-off-by: York Sun

Driver/DDR: Add Freescale DDR driver for ARM

2013-11-25T19:43:46+00:00

Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.

Signed-off-by: York Sun

Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx

2013-11-25T19:43:46+00:00

Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun

Driver/DDR: Moving Freescale DDR driver to a common driver

2013-11-25T19:43:43+00:00

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun