u-boot.git/drivers/ddr, branch v2014.07 Unnamed repository; edit this file 'description' to name the repository. driver/ddr/fsl: Fix printing unspecified module info for DDR4 2014-06-05T20:45:07+00:00 York Sun yorksun@freescale.com 2014-06-05T19:32:15+00:00 353527d527b78297571c05b8a1687c92d42f6d20 The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun <yorksun@freescale.com> 
The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Add workaround for DDR erratum A004508 2014-06-05T20:45:07+00:00 York Sun yorksun@freescale.com 2014-05-23T20:15:00+00:00 9855b3beca648dabe4d86b06d36bf219ebd0732d When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com> 
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
Add cli_ prefix to readline functions 2014-05-29T21:45:31+00:00 Simon Glass sjg@chromium.org 2014-04-11T02:01:27+00:00 e1bf824dfd6881f6f633238c275bfa1e5d83c433 This makes it clear where the code resides. Signed-off-by: Simon Glass <sjg@chromium.org> 
This makes it clear where the code resides.

Signed-off-by: Simon Glass <sjg@chromium.org>
move CLI prototypes to cli.h and add comments 2014-05-29T21:45:31+00:00 Simon Glass sjg@chromium.org 2014-04-11T02:01:25+00:00 18d66533ac773f59efc93e5c19971fad5e6af82f Move the CLI prototypes from common.h to cli.h as part of an effort to reduce the size of common.h. Signed-off-by: Simon Glass <sjg@chromium.org> 
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
mpc85xx/t104x: Add deep sleep framework support 2014-04-23T00:58:49+00:00 Tang Yuantian yuantian.tang@freescale.com 2014-04-17T07:33:46+00:00 aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/ddr: Fix possible out of bounds error 2014-04-23T00:58:49+00:00 York Sun yorksun@freescale.com 2014-04-01T21:20:49+00:00 349689b8021f0a7d7923099bd8bbe5eab117d4fa This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Add DDR4 support to Freescale DDR driver 2014-04-23T00:58:48+00:00 York Sun yorksun@freescale.com 2014-03-28T00:54:47+00:00 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com> 
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr: Add 256 byte interleaving support 2014-02-21T16:06:13+00:00 York Sun yorksun@freescale.com 2014-02-10T21:59:44+00:00 6b1e1254f326940e5b65c7029f71b964bdf28fd4 Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com> 
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
Driver/ddr: Add support of different DDR base address 2014-02-21T16:06:13+00:00 York Sun yorksun@freescale.com 2014-02-10T21:59:43+00:00 6b9e309a8a7f0f33252288f0ed8794a83a488301 DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com> 
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr: Change Freescale ARM DDR driver to support both big and little endian 2014-02-21T16:06:13+00:00 York Sun yorksun@freescale.com 2014-02-10T21:59:42+00:00 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com> 
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>