u-boot.git/drivers/ddr, branch v2014.07-rc2

mpc85xx/t104x: Add deep sleep framework support

2014-04-23T00:58:49Z

When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian Reviewed-by: York Sun

drivers/ddr: Fix possible out of bounds error

2014-04-23T00:58:49Z

This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun Reviewed-by: York Sun

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

2014-04-23T00:58:48Z

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun

driver/ddr: Add 256 byte interleaving support

2014-02-21T16:06:13Z

Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun

Driver/ddr: Add support of different DDR base address

2014-02-21T16:06:13Z

DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun

driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

2014-02-21T16:06:13Z

Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun

powerpc/mpc85xx: Revise workaround for DDR-A003

2014-01-21T21:40:52Z

Existing workaround only handles one RDIMM on reference design. In case of two RDIMMs being used, the workaround requires two separate writes to DDR_SDRAM_MD_CNTL register. This patch also restores two debug registers changed by the workaround. Signed-off-by: York Sun CC: Ben Collins CC: James Yang

Driver/DDR: Update DDR driver to allow non-zero base address

2013-11-25T19:43:47Z

The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun

powerpc/mpc8xxx: Extend DDR registers' fields

2013-11-25T19:43:46Z

Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun

Driver/DDR: Add Freescale DDR driver for ARM

2013-11-25T19:43:46Z

Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun