u-boot.git/drivers/ddr, branch v2014.10

driver/ddr/fsl: Fix DDR4 driver

2014-09-25T15:36:20+00:00

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun

driver/ddr/fsl: Fix tXP and tCKE

2014-09-25T15:36:18+00:00

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun

driver/ddr: Restruct driver to allow standalone memory space

2014-09-25T15:36:18+00:00

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun

driver/ddr/fsl: Add support of overriding chip select write leveling

2014-09-08T17:30:34+00:00

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun

driver/ddr/freescale: Fix DDR3 driver for ARM

2014-09-08T17:30:34+00:00

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun

driver/ddr/freescale: Add support of accumulate ECC

2014-09-08T17:30:34+00:00

If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.

Signed-off-by: York Sun

driver/ddr: Fix DDR register timing_cfg_8

2014-07-22T23:25:55+00:00

The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun

driver/ddr: Fix DDR4 driver for ARM

2014-07-22T23:25:54+00:00

Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun

driver/ddr/fsl: Fix printing unspecified module info for DDR4

2014-06-05T20:45:07+00:00

The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun

powerpc/mpc85xx: Add workaround for DDR erratum A004508

2014-06-05T20:45:07+00:00

When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun