u-boot.git/drivers/ddr, branch v2014.10-rc2Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/ddr?h=v2014.10-rc22014-07-22T23:25:55Zdriver/ddr: Fix DDR register timing_cfg_82014-07-22T23:25:55ZYork Sunyorksun@freescale.com2014-06-26T18:14:44Zurn:sha1:3d75ec95f57224995210db5c5dea8d458cf862fb
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.
Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr: Fix DDR4 driver for ARM2014-07-22T23:25:54ZYork Sunyorksun@freescale.com2014-06-23T22:36:44Zurn:sha1:8340e7ac86ad3c59956e8f0bd627b741e5209439
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Fix printing unspecified module info for DDR42014-06-05T20:45:07ZYork Sunyorksun@freescale.com2014-06-05T19:32:15Zurn:sha1:353527d527b78297571c05b8a1687c92d42f6d20
The offset of module information is at 128, different from DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Add workaround for DDR erratum A0045082014-06-05T20:45:07ZYork Sunyorksun@freescale.com2014-05-23T20:15:00Zurn:sha1:9855b3beca648dabe4d86b06d36bf219ebd0732d
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
Add cli_ prefix to readline functions2014-05-29T21:45:31ZSimon Glasssjg@chromium.org2014-04-11T02:01:27Zurn:sha1:e1bf824dfd6881f6f633238c275bfa1e5d83c433
This makes it clear where the code resides.
Signed-off-by: Simon Glass <sjg@chromium.org>
move CLI prototypes to cli.h and add comments2014-05-29T21:45:31ZSimon Glasssjg@chromium.org2014-04-11T02:01:25Zurn:sha1:18d66533ac773f59efc93e5c19971fad5e6af82f
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.
Signed-off-by: Simon Glass <sjg@chromium.org>
mpc85xx/t104x: Add deep sleep framework support2014-04-23T00:58:49ZTang Yuantianyuantian.tang@freescale.com2014-04-17T07:33:46Zurn:sha1:aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/ddr: Fix possible out of bounds error2014-04-23T00:58:49ZYork Sunyorksun@freescale.com2014-04-01T21:20:49Zurn:sha1:349689b8021f0a7d7923099bd8bbe5eab117d4fa
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.
Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Add DDR4 support to Freescale DDR driver2014-04-23T00:58:48ZYork Sunyorksun@freescale.com2014-03-28T00:54:47Zurn:sha1:34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.
Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr: Add 256 byte interleaving support2014-02-21T16:06:13ZYork Sunyorksun@freescale.com2014-02-10T21:59:44Zurn:sha1:6b1e1254f326940e5b65c7029f71b964bdf28fd4
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.
Signed-off-by: York Sun <yorksun@freescale.com>