u-boot.git/drivers/ddr, branch v2015.01

driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

2014-12-15T17:15:12+00:00

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun

fsl/sleep: updated the deep sleep framework for QorIQ platforms

2014-12-11T17:41:18+00:00

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian 
Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for faulty SPD

2014-12-05T16:06:14+00:00

Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun

driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

2014-12-05T16:06:11+00:00

Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun

linux/kernel.h: sync min, max, min3, max3 macros with Linux

2014-11-23T11:48:30+00:00

U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada 
Acked-by: Pavel Machek 
Acked-by: Lukasz Majewski 
Tested-by: Lukasz Majewski 
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini

driver/ddr/fsl: Fix DDR4 driver

2014-09-25T15:36:20+00:00

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun

driver/ddr/fsl: Fix tXP and tCKE

2014-09-25T15:36:18+00:00

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun

driver/ddr: Restruct driver to allow standalone memory space

2014-09-25T15:36:18+00:00

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun

driver/ddr/fsl: Add support of overriding chip select write leveling

2014-09-08T17:30:34+00:00

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun

driver/ddr/freescale: Fix DDR3 driver for ARM

2014-09-08T17:30:34+00:00

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun