u-boot.git/drivers/ddr, branch v2015.07

arm: mvebu: db-mv784mp-gp: Fix ECC I2C address

2015-05-05T12:32:05+00:00

The macro to select the I2C address for ECC bus-width detection
was defined incorrectly for the Marvell DB-MV784MP-GP board. This
patch changes the macro to the correct value to fix this issue.

Signed-off-by: Stefan Roese

driver/ddr/fsl: Add workaround for DDR erratum A008511

2015-04-23T15:55:54+00:00

This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.

Signed-off-by: York Sun

driver/ddr/fsl: Add built-in memory test for DDR4 driver

2015-04-23T15:55:53+00:00

Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.

Signed-off-by: York Sun

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23T15:55:53+00:00

CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.

Signed-off-by: York Sun

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53+00:00

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun

MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register

2015-04-20T17:15:28+00:00

According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section 9.4.1.8 of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source
       synchronously.

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit
457caecdbca3df21a93abff19eab12dbc61b7897.

Testing Done:

Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.

Signed-off-by: Curt Brune 
Reviewed-by: York Sun

driver/ddr/fsl: Add sync of refresh

2015-02-24T21:09:42+00:00

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun

driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation

2015-02-24T21:09:26+00:00

wwt_bg should match rrt_bg. It was a typo in driver.

Signed-off-by: York Sun

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24T21:09:18+00:00

Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.

Signed-off-by: York Sun

driver/ddr/fsl: Add workround for erratumn A008514

2015-02-24T21:09:10+00:00

Erratum A008514 workround requires writing register eddrtqcr1 with
value 0x63b20002.

Signed-off-by: York Sun