u-boot.git/drivers/ddr, branch v2016.01 Unnamed repository; edit this file 'description' to name the repository. move erratum a008336 and a008514 to soc specific file 2015-12-15T00:57:32+00:00 Yao Yuan yao.yuan@freescale.com 2015-12-05T06:59:14+00:00 000f4e7686f4291fbd74d8920b586caf10f9241f As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
fsl/ddr: updated ddr errata-A008378 for arm and power SoCs 2015-12-14T02:27:28+00:00 Shengzhou Liu Shengzhou.Liu@freescale.com 2015-11-20T07:52:04+00:00 a46b1852de967f8a7de26e0b46e864c794a18c16 DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Update timing config for heavy load 2015-12-14T02:27:27+00:00 York Sun yorksun@freescale.com 2015-11-04T18:03:21+00:00 6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3 In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun <yorksun@freescale.com> 
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Update workaround for A008511 for vref range 2015-12-14T02:27:27+00:00 York Sun yorksun@freescale.com 2015-11-04T18:03:20+00:00 7cc079989d4e99968f0efb08eff1cd342ce26ac3 The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com> 
The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Update MR5 RTT park 2015-12-14T02:27:27+00:00 York Sun yorksun@freescale.com 2015-11-04T18:03:19+00:00 8a51429e0094746c035ba96af5999432b3b3480b For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com> 
For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Update DDR4 MR6 for Vref range 2015-12-14T02:27:27+00:00 York Sun yorksun@freescale.com 2015-11-04T18:03:18+00:00 0fb7197436378eeb92ff8e2c6a6f6490b31eef1c MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com> 
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
driver/ddr/fsl: Update DDR4 RTT values 2015-12-14T02:27:27+00:00 York Sun yorksun@freescale.com 2015-11-04T18:03:17+00:00 19601dd99c8169e27457a96f03f0c3fef908a4c6 DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com> 
DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl: Fix typo in BIST test for DDR4 2015-11-30T17:11:12+00:00 York Sun yorksun@freescale.com 2015-11-06T17:58:46+00:00 da305b9f57cd459a26d276390f699666a5d8bc4f BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> 
BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 2015-11-30T17:11:11+00:00 York Sun yorksun@freescale.com 2015-11-04T17:53:10+00:00 61bd2f75f5eaf645e2c90fe2294cba37f7d8627f Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com> 
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
armv8: ls2085a: Add support of LS2085A SoC 2015-11-30T17:10:47+00:00 Prabhakar Kushwaha prabhakar@freescale.com 2015-11-09T11:12:20+00:00 06b53010436bd7d4d0da6bdb2f505131a094abc6 Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com> 
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>