u-boot.git/drivers/ddr, branch v2016.03

Use correct spelling of "U-Boot"

2016-02-06T11:00:59+00:00

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng 
Reviewed-by: Heiko Schocher 
Reviewed-by: Simon Glass 
Reviewed-by: Minkyu Kang

drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

2016-02-01T21:14:01+00:00

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker 
Signed-off-by: Purna Chandra Mandal 
Reviewed-by: Daniel Schwierzeck 
Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass

drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers

2016-01-25T16:24:16+00:00

Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.

Signed-off-by: Ed Swarthout 
Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for A009663

2016-01-25T16:24:15+00:00

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

fsl/ddr: Add workaround for ERRATUM_A009942

2016-01-25T16:24:14+00:00

During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

Add more SPDX-License-Identifier tags

2016-01-19T13:31:21+00:00

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini

ddr: altera: Init the rule ID in debug code

2016-01-16T06:07:22+00:00

Init the rule ID, otherwise the debug code will always dump the
protection settings entry 0.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen

mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT

2016-01-14T13:08:59+00:00

This should make it clear that this symbol is meant to be defined by
board headers.

Signed-off-by: Phil Sutter 
Acked-by: Stefan Roese 
Reviewed-by: Tom Rini

axp: Fix debugging support in DDR3 write leveling

2016-01-14T13:08:59+00:00

If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing.
In addition to that, get rid of debug output printing non-existent
counter variable.

Signed-off-by: Phil Sutter 
Acked-by: Stefan Roese 
Reviewed-by: Tom Rini

arm: mvebu: Make ECC support configurable on Armada XP

2016-01-14T13:08:59+00:00

Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
Cc: Phil Sutter