u-boot.git/drivers/ddr, branch v2016.05

Fix spelling of "occurred".

2016-05-02T22:37:09+00:00

Signed-off-by: Vagrant Cascadian 
Reviewed-by: Simon Glass

ddr: altera: Repair DQ window centering code

2016-04-20T09:28:45+00:00

The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Staticize global variables

2016-04-20T09:28:45+00:00

Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Make DLEVEL behavior inclusive

2016-04-20T09:28:45+00:00

Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

2016-04-20T09:28:45+00:00

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Remove unnecessary ODT mode config

2016-04-20T09:28:44+00:00

There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Remove unnecessary update of the SCC

2016-04-20T09:28:44+00:00

Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Fix DRAM end value in protection rule

2016-04-20T09:28:44+00:00

The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Fix scc_mgr_set() argument order

2016-04-20T09:28:44+00:00

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See

ddr: altera: Tweak DQS tracking enable handling

2016-04-20T09:28:44+00:00

In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See