u-boot.git/drivers/ddr, branch v2016.05-rc1

Fix typo choosen in comments and printf logs

2016-03-27T13:12:23Z

Minor change: chosen is written with one "o". No code change here, only comment & printf. Signed-off-by: Alexander Merkle Reviewed-by: Bin Meng

arm: mvebu: Fix ddr3_init() cpu config

2016-03-24T08:36:40Z

Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese

driver/ddr/fsl: Add workaround for erratum A-009803

2016-03-21T19:42:13Z

During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

2016-03-21T19:42:13Z

Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

Use correct spelling of "U-Boot"

2016-02-06T11:00:59Z

Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng Reviewed-by: Heiko Schocher Reviewed-by: Simon Glass Reviewed-by: Minkyu Kang

drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

2016-02-01T21:14:01Z

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker Signed-off-by: Purna Chandra Mandal Reviewed-by: Daniel Schwierzeck Reviewed-by: Tom Rini Reviewed-by: Simon Glass

drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers

2016-01-25T16:24:16Z

Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for A009663

2016-01-25T16:24:15Z

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

fsl/ddr: Add workaround for ERRATUM_A009942

2016-01-25T16:24:14Z

During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun

Add more SPDX-License-Identifier tags

2016-01-19T13:31:21Z

In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini