u-boot.git/drivers/ddr, branch v2016.07

driver/ddr/fsl: Check condition for erratum A-009803

2016-06-03T21:12:49+00:00

Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

drivers/ddr/fsl: Disabling data init if ECC is not enabled

2016-06-03T21:12:48+00:00

If ECC is not enabled, data init can be disabled to speed up booting.

Signed-off-by: York Sun

drivers/ddr/fsl: Fix timing_cfg_2 register

2016-06-03T21:12:06+00:00

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

2016-06-03T21:06:35+00:00

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-05-24T17:42:03+00:00

arm: mvebu: a38x: Weed out floating point use

2016-05-20T09:01:00+00:00

For reason unknown, recently, the DDR init code writers are really fond
of hiding some small floating point operating deep in their creations.
This patch removes one from the Marvell A38x code.

Instead of returning size of chip as float from ddr3_get_device_size()
in GiB units, return it as int in MiB units. Since this would interfere
with the huge switch code in ddr3_calc_mem_cs_size(), rework the code
to match the change.

Before this patch, the cs_mem_size variable could have these values:
 ( { 16, 32 } x { 8, 16 } x { 0.01, 0.5, 1, 2, 4, 8 } ) / 8 =
   { 0.000000, 0.001250, 0.002500, 0.005000, 0.062500, 0.125000,
     0.250000, 0.500000, 1.000000, 2.000000, 4.000000, }
The switch code checked for a subset of the resulting RAM sizes, which
is in range 128 MiB ... 2048 MiB.

With this patch, the cs_mem_size variable can have these values:
 ( { 16, 32 } x { 8, 16 } x { 0, 512, 1024, 2048, 4096, 8192 } ) / 8 =
   { 0, 64, 128, 256, 512, 1024, 2048, 4096 }
To retain previous behavior, filter out 0 MiB (invalid size), 64 MiB
and 4096 MiB options.

Removing the floating point stuff also saves 1.5k from text segment:
  clearfog       :  spl/u-boot-spl:all -1592  spl/u-boot-spl:text -1592

Signed-off-by: Marek Vasut 
Cc: Dirk Eibach 
Cc: Stefan Roese 
Signed-off-by: Stefan Roese

driver/ddr/fsl: Add workaround for erratum A-010165

2016-05-18T15:51:47+00:00

During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

driver/ddr/fsl: Add workaround for erratum A-009801

2016-05-17T16:26:53+00:00

The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

drivers/ddr/fsl: update workaround for erratum A-008511

2016-05-17T16:26:42+00:00

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

Fix spelling of "occurred".

2016-05-02T22:37:09+00:00

Signed-off-by: Vagrant Cascadian 
Reviewed-by: Simon Glass