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<title>u-boot.git/drivers/ddr, branch v2017.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS</title>
<updated>2017-01-05T00:40:52+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:45+00:00</published>
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<id>51370d561842ae7438337e77a93177e13796ac45</id>
<content type='text'>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig</title>
<updated>2017-01-05T00:40:49+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:44+00:00</published>
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<id>66e399b68d20d96a90ba391d75c2290bd63bf4a5</id>
<content type='text'>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig</title>
<updated>2017-01-05T00:40:46+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=63659ff317c72ff6d74a3147ad758c5904b034bc'/>
<id>63659ff317c72ff6d74a3147ad758c5904b034bc</id>
<content type='text'>
Use Kconfig to select errata workaround.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Use Kconfig to select errata workaround.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig</title>
<updated>2017-01-05T00:40:42+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba1b6fb5cc86cb603c396d465cf5dac11ccab0b3'/>
<id>ba1b6fb5cc86cb603c396d465cf5dac11ccab0b3</id>
<content type='text'>
Use Kconfig to select errata workaround.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Use Kconfig to select errata workaround.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl_ddr: Move DDR config options to driver Kconfig</title>
<updated>2017-01-05T00:40:41+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-12-28T16:43:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff'/>
<id>d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff</id>
<content type='text'>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum</title>
<updated>2016-12-05T16:31:45+00:00</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@nxp.com</email>
</author>
<published>2016-11-21T03:36:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=02fb2761576be8096ebf1b3f961a2cdb21b422ae'/>
<id>02fb2761576be8096ebf1b3f961a2cdb21b422ae</id>
<content type='text'>
- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/ddr: Fix compiling warning</title>
<updated>2016-12-05T16:31:45+00:00</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@nxp.com</email>
</author>
<published>2016-11-21T03:36:47+00:00</published>
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<id>5a17b8b5dab8973089b7400d05f8503d56f29370</id>
<content type='text'>
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: MPC8555: Remove macro CONFIG_MPC8555</title>
<updated>2016-11-24T07:42:05+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-11-16T19:23:23+00:00</published>
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<id>3c3d8ab58d40d39830de7aed3f4b7110067d7d2d</id>
<content type='text'>
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
<content type='xhtml'>
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<pre>
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: mpc8541: Remove macro CONFIG_MPC8541</title>
<updated>2016-11-24T07:42:05+00:00</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-11-16T19:18:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3aff30825eba88ab57f6fc2182ceef288c8aaafc'/>
<id>3aff30825eba88ab57f6fc2182ceef288c8aaafc</id>
<content type='text'>
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
<content type='xhtml'>
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<pre>
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ddr: altera: Configuring SDRAM extra cycles timing parameters</title>
<updated>2016-10-27T06:03:07+00:00</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2016-09-21T02:25:56+00:00</published>
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<id>89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd</id>
<content type='text'>
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
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<pre>
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
</pre>
</div>
</content>
</entry>
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