u-boot.git/drivers/ddr, branch v2019.10

ddr, fsl: add DM_I2C support

2019-08-26T15:46:24Z

add DM_I2C support for this driver. Signed-off-by: Heiko Schocher Reviewed-by: Prabhakar Kushwaha

boards: lx2160a: Add support of I2C driver model

2019-08-22T03:37:35Z

DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha

env: Move env_get_f() to env.h

2019-08-11T20:43:41Z

Move this function over to the new header file. Signed-off-by: Simon Glass Acked-by: Joe Hershberger

dm: ddr: socfpga: fix gen5 ddr driver to not use bss

2019-07-21T10:45:01Z

This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt

mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

2019-05-21T05:52:33Z

CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six

arm: socfpga: Move Stratix 10 SDRAM driver to DM

2019-05-06T10:44:17Z

Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan

ddr: altera: Compile ALTERA SDRAM in SPL only

2019-05-06T10:44:17Z

Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan

ddr: imx8m: hide i.MX8M DDR options from device driver entry

2019-04-25T17:20:04Z

Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan

ddr: altera: Stratix10: Add ECC memory scrubbing

2019-04-17T20:20:17Z

Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan

ddr: altera: Stratix10: Add multi-banks DRAM size check

2019-04-17T20:20:17Z

Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan